1 #ifndef _ASM_X86_MACH_DEFAULT_MACH_APIC_H
2 #define _ASM_X86_MACH_DEFAULT_MACH_APIC_H
3
4 #ifdef CONFIG_X86_LOCAL_APIC
5
6 #include <mach_apicdef.h>
7 #include <asm/smp.h>
8
9 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
10
target_cpus(void)11 static inline const struct cpumask *target_cpus(void)
12 {
13 #ifdef CONFIG_SMP
14 return cpu_online_mask;
15 #else
16 return cpumask_of(0);
17 #endif
18 }
19
20 #define NO_BALANCE_IRQ (0)
21 #define esr_disable (0)
22
23 #ifdef CONFIG_X86_64
24 #include <asm/genapic.h>
25 #define INT_DELIVERY_MODE (genapic->int_delivery_mode)
26 #define INT_DEST_MODE (genapic->int_dest_mode)
27 #define TARGET_CPUS (genapic->target_cpus())
28 #define apic_id_registered (genapic->apic_id_registered)
29 #define init_apic_ldr (genapic->init_apic_ldr)
30 #define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid)
31 #define cpu_mask_to_apicid_and (genapic->cpu_mask_to_apicid_and)
32 #define phys_pkg_id (genapic->phys_pkg_id)
33 #define vector_allocation_domain (genapic->vector_allocation_domain)
34 #define read_apic_id() (GET_APIC_ID(apic_read(APIC_ID)))
35 #define send_IPI_self (genapic->send_IPI_self)
36 #define wakeup_secondary_cpu (genapic->wakeup_cpu)
37 extern void setup_apic_routing(void);
38 #else
39 #define INT_DELIVERY_MODE dest_LowestPrio
40 #define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */
41 #define TARGET_CPUS (target_cpus())
42 #define wakeup_secondary_cpu wakeup_secondary_cpu_via_init
43 /*
44 * Set up the logical destination ID.
45 *
46 * Intel recommends to set DFR, LDR and TPR before enabling
47 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
48 * document number 292116). So here it goes...
49 */
init_apic_ldr(void)50 static inline void init_apic_ldr(void)
51 {
52 unsigned long val;
53
54 apic_write(APIC_DFR, APIC_DFR_VALUE);
55 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
56 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
57 apic_write(APIC_LDR, val);
58 }
59
apic_id_registered(void)60 static inline int apic_id_registered(void)
61 {
62 return physid_isset(read_apic_id(), phys_cpu_present_map);
63 }
64
cpu_mask_to_apicid(const struct cpumask * cpumask)65 static inline unsigned int cpu_mask_to_apicid(const struct cpumask *cpumask)
66 {
67 return cpumask_bits(cpumask)[0];
68 }
69
cpu_mask_to_apicid_and(const struct cpumask * cpumask,const struct cpumask * andmask)70 static inline unsigned int cpu_mask_to_apicid_and(const struct cpumask *cpumask,
71 const struct cpumask *andmask)
72 {
73 unsigned long mask1 = cpumask_bits(cpumask)[0];
74 unsigned long mask2 = cpumask_bits(andmask)[0];
75 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
76
77 return (unsigned int)(mask1 & mask2 & mask3);
78 }
79
phys_pkg_id(u32 cpuid_apic,int index_msb)80 static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
81 {
82 return cpuid_apic >> index_msb;
83 }
84
setup_apic_routing(void)85 static inline void setup_apic_routing(void)
86 {
87 #ifdef CONFIG_X86_IO_APIC
88 printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
89 "Flat", nr_ioapics);
90 #endif
91 }
92
apicid_to_node(int logical_apicid)93 static inline int apicid_to_node(int logical_apicid)
94 {
95 #ifdef CONFIG_SMP
96 return apicid_2_node[hard_smp_processor_id()];
97 #else
98 return 0;
99 #endif
100 }
101
vector_allocation_domain(int cpu,struct cpumask * retmask)102 static inline void vector_allocation_domain(int cpu, struct cpumask *retmask)
103 {
104 /* Careful. Some cpus do not strictly honor the set of cpus
105 * specified in the interrupt destination when using lowest
106 * priority interrupt delivery mode.
107 *
108 * In particular there was a hyperthreading cpu observed to
109 * deliver interrupts to the wrong hyperthread when only one
110 * hyperthread was specified in the interrupt desitination.
111 */
112 *retmask = (cpumask_t) { { [0] = APIC_ALL_CPUS } };
113 }
114 #endif
115
check_apicid_used(physid_mask_t bitmap,int apicid)116 static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
117 {
118 return physid_isset(apicid, bitmap);
119 }
120
check_apicid_present(int bit)121 static inline unsigned long check_apicid_present(int bit)
122 {
123 return physid_isset(bit, phys_cpu_present_map);
124 }
125
ioapic_phys_id_map(physid_mask_t phys_map)126 static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
127 {
128 return phys_map;
129 }
130
multi_timer_check(int apic,int irq)131 static inline int multi_timer_check(int apic, int irq)
132 {
133 return 0;
134 }
135
136 /* Mapping from cpu number to logical apicid */
cpu_to_logical_apicid(int cpu)137 static inline int cpu_to_logical_apicid(int cpu)
138 {
139 return 1 << cpu;
140 }
141
cpu_present_to_apicid(int mps_cpu)142 static inline int cpu_present_to_apicid(int mps_cpu)
143 {
144 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
145 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
146 else
147 return BAD_APICID;
148 }
149
apicid_to_cpu_present(int phys_apicid)150 static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
151 {
152 return physid_mask_of_physid(phys_apicid);
153 }
154
setup_portio_remap(void)155 static inline void setup_portio_remap(void)
156 {
157 }
158
check_phys_apicid_present(int boot_cpu_physical_apicid)159 static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
160 {
161 return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
162 }
163
enable_apic_mode(void)164 static inline void enable_apic_mode(void)
165 {
166 }
167 #endif /* CONFIG_X86_LOCAL_APIC */
168 #endif /* _ASM_X86_MACH_DEFAULT_MACH_APIC_H */
169