1 /* 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 3 */ 4 #ifndef _ASM_POWERPC_PPC_ASM_H 5 #define _ASM_POWERPC_PPC_ASM_H 6 7 #include <linux/stringify.h> 8 #include <asm/asm-compat.h> 9 #include <asm/processor.h> 10 11 #ifndef __ASSEMBLY__ 12 #error __FILE__ should only be used in assembler files 13 #else 14 15 #define SZL (BITS_PER_LONG/8) 16 17 /* 18 * Stuff for accurate CPU time accounting. 19 * These macros handle transitions between user and system state 20 * in exception entry and exit and accumulate time to the 21 * user_time and system_time fields in the paca. 22 */ 23 24 #ifndef CONFIG_VIRT_CPU_ACCOUNTING 25 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) 26 #define ACCOUNT_CPU_USER_EXIT(ra, rb) 27 #else 28 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) \ 29 beq 2f; /* if from kernel mode */ \ 30 BEGIN_FTR_SECTION; \ 31 mfspr ra,SPRN_PURR; /* get processor util. reg */ \ 32 END_FTR_SECTION_IFSET(CPU_FTR_PURR); \ 33 BEGIN_FTR_SECTION; \ 34 MFTB(ra); /* or get TB if no PURR */ \ 35 END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \ 36 ld rb,PACA_STARTPURR(r13); \ 37 std ra,PACA_STARTPURR(r13); \ 38 subf rb,rb,ra; /* subtract start value */ \ 39 ld ra,PACA_USER_TIME(r13); \ 40 add ra,ra,rb; /* add on to user time */ \ 41 std ra,PACA_USER_TIME(r13); \ 42 2: 43 44 #define ACCOUNT_CPU_USER_EXIT(ra, rb) \ 45 BEGIN_FTR_SECTION; \ 46 mfspr ra,SPRN_PURR; /* get processor util. reg */ \ 47 END_FTR_SECTION_IFSET(CPU_FTR_PURR); \ 48 BEGIN_FTR_SECTION; \ 49 MFTB(ra); /* or get TB if no PURR */ \ 50 END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \ 51 ld rb,PACA_STARTPURR(r13); \ 52 std ra,PACA_STARTPURR(r13); \ 53 subf rb,rb,ra; /* subtract start value */ \ 54 ld ra,PACA_SYSTEM_TIME(r13); \ 55 add ra,ra,rb; /* add on to user time */ \ 56 std ra,PACA_SYSTEM_TIME(r13); 57 #endif 58 59 /* 60 * Macros for storing registers into and loading registers from 61 * exception frames. 62 */ 63 #ifdef __powerpc64__ 64 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) 65 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) 66 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) 67 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) 68 #else 69 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) 70 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) 71 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \ 72 SAVE_10GPRS(22, base) 73 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \ 74 REST_10GPRS(22, base) 75 #endif 76 77 /* 78 * Define what the VSX XX1 form instructions will look like, then add 79 * the 128 bit load store instructions based on that. 80 */ 81 #define VSX_XX1(xs, ra, rb) (((xs) & 0x1f) << 21 | ((ra) << 16) | \ 82 ((rb) << 11) | (((xs) >> 5))) 83 84 #define STXVD2X(xs, ra, rb) .long (0x7c000798 | VSX_XX1((xs), (ra), (rb))) 85 #define LXVD2X(xs, ra, rb) .long (0x7c000698 | VSX_XX1((xs), (ra), (rb))) 86 87 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) 88 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) 89 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) 90 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) 91 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) 92 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) 93 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) 94 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) 95 96 #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) 97 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 98 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 99 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 100 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 101 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 102 #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) 103 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 104 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 105 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 106 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 107 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 108 109 #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base 110 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 111 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) 112 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) 113 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) 114 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) 115 #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base 116 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 117 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) 118 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) 119 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 120 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 121 122 /* Save the lower 32 VSRs in the thread VSR region */ 123 #define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,b,base) 124 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 125 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 126 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 127 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 128 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 129 #define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,b,base) 130 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 131 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 132 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 133 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 134 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 135 /* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */ 136 #define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,b,base) 137 #define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base) 138 #define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base) 139 #define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base) 140 #define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base) 141 #define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base) 142 #define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,b,base) 143 #define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base) 144 #define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base) 145 #define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base) 146 #define REST_16VSRSU(n,b,base) REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base) 147 #define REST_32VSRSU(n,b,base) REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base) 148 149 #define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base) 150 #define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base) 151 #define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base) 152 #define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base) 153 #define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base) 154 #define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base) 155 #define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n 156 #define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base) 157 #define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base) 158 #define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base) 159 #define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base) 160 #define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base) 161 162 /* Macros to adjust thread priority for hardware multithreading */ 163 #define HMT_VERY_LOW or 31,31,31 # very low priority 164 #define HMT_LOW or 1,1,1 165 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 166 #define HMT_MEDIUM or 2,2,2 167 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 168 #define HMT_HIGH or 3,3,3 169 170 /* handle instructions that older assemblers may not know */ 171 #define RFCI .long 0x4c000066 /* rfci instruction */ 172 #define RFDI .long 0x4c00004e /* rfdi instruction */ 173 #define RFMCI .long 0x4c00004c /* rfmci instruction */ 174 175 #ifdef __KERNEL__ 176 #ifdef CONFIG_PPC64 177 178 #define XGLUE(a,b) a##b 179 #define GLUE(a,b) XGLUE(a,b) 180 181 #define _GLOBAL(name) \ 182 .section ".text"; \ 183 .align 2 ; \ 184 .globl name; \ 185 .globl GLUE(.,name); \ 186 .section ".opd","aw"; \ 187 name: \ 188 .quad GLUE(.,name); \ 189 .quad .TOC.@tocbase; \ 190 .quad 0; \ 191 .previous; \ 192 .type GLUE(.,name),@function; \ 193 GLUE(.,name): 194 195 #define _INIT_GLOBAL(name) \ 196 .section ".text.init.refok"; \ 197 .align 2 ; \ 198 .globl name; \ 199 .globl GLUE(.,name); \ 200 .section ".opd","aw"; \ 201 name: \ 202 .quad GLUE(.,name); \ 203 .quad .TOC.@tocbase; \ 204 .quad 0; \ 205 .previous; \ 206 .type GLUE(.,name),@function; \ 207 GLUE(.,name): 208 209 #define _KPROBE(name) \ 210 .section ".kprobes.text","a"; \ 211 .align 2 ; \ 212 .globl name; \ 213 .globl GLUE(.,name); \ 214 .section ".opd","aw"; \ 215 name: \ 216 .quad GLUE(.,name); \ 217 .quad .TOC.@tocbase; \ 218 .quad 0; \ 219 .previous; \ 220 .type GLUE(.,name),@function; \ 221 GLUE(.,name): 222 223 #define _STATIC(name) \ 224 .section ".text"; \ 225 .align 2 ; \ 226 .section ".opd","aw"; \ 227 name: \ 228 .quad GLUE(.,name); \ 229 .quad .TOC.@tocbase; \ 230 .quad 0; \ 231 .previous; \ 232 .type GLUE(.,name),@function; \ 233 GLUE(.,name): 234 235 #define _INIT_STATIC(name) \ 236 .section ".text.init.refok"; \ 237 .align 2 ; \ 238 .section ".opd","aw"; \ 239 name: \ 240 .quad GLUE(.,name); \ 241 .quad .TOC.@tocbase; \ 242 .quad 0; \ 243 .previous; \ 244 .type GLUE(.,name),@function; \ 245 GLUE(.,name): 246 247 #else /* 32-bit */ 248 249 #define _ENTRY(n) \ 250 .globl n; \ 251 n: 252 253 #define _GLOBAL(n) \ 254 .text; \ 255 .stabs __stringify(n:F-1),N_FUN,0,0,n;\ 256 .globl n; \ 257 n: 258 259 #define _KPROBE(n) \ 260 .section ".kprobes.text","a"; \ 261 .globl n; \ 262 n: 263 264 #endif 265 266 /* 267 * LOAD_REG_IMMEDIATE(rn, expr) 268 * Loads the value of the constant expression 'expr' into register 'rn' 269 * using immediate instructions only. Use this when it's important not 270 * to reference other data (i.e. on ppc64 when the TOC pointer is not 271 * valid) and when 'expr' is a constant or absolute address. 272 * 273 * LOAD_REG_ADDR(rn, name) 274 * Loads the address of label 'name' into register 'rn'. Use this when 275 * you don't particularly need immediate instructions only, but you need 276 * the whole address in one register (e.g. it's a structure address and 277 * you want to access various offsets within it). On ppc32 this is 278 * identical to LOAD_REG_IMMEDIATE. 279 * 280 * LOAD_REG_ADDRBASE(rn, name) 281 * ADDROFF(name) 282 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 283 * register 'rn'. ADDROFF(name) returns the remainder of the address as 284 * a constant expression. ADDROFF(name) is a signed expression < 16 bits 285 * in size, so is suitable for use directly as an offset in load and store 286 * instructions. Use this when loading/storing a single word or less as: 287 * LOAD_REG_ADDRBASE(rX, name) 288 * ld rY,ADDROFF(name)(rX) 289 */ 290 #ifdef __powerpc64__ 291 #define LOAD_REG_IMMEDIATE(reg,expr) \ 292 lis (reg),(expr)@highest; \ 293 ori (reg),(reg),(expr)@higher; \ 294 rldicr (reg),(reg),32,31; \ 295 oris (reg),(reg),(expr)@h; \ 296 ori (reg),(reg),(expr)@l; 297 298 #define LOAD_REG_ADDR(reg,name) \ 299 ld (reg),name@got(r2) 300 301 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 302 #define ADDROFF(name) 0 303 304 /* offsets for stack frame layout */ 305 #define LRSAVE 16 306 307 #else /* 32-bit */ 308 309 #define LOAD_REG_IMMEDIATE(reg,expr) \ 310 lis (reg),(expr)@ha; \ 311 addi (reg),(reg),(expr)@l; 312 313 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name) 314 315 #define LOAD_REG_ADDRBASE(reg, name) lis (reg),name@ha 316 #define ADDROFF(name) name@l 317 318 /* offsets for stack frame layout */ 319 #define LRSAVE 4 320 321 #endif 322 323 /* various errata or part fixups */ 324 #ifdef CONFIG_PPC601_SYNC_FIX 325 #define SYNC \ 326 BEGIN_FTR_SECTION \ 327 sync; \ 328 isync; \ 329 END_FTR_SECTION_IFSET(CPU_FTR_601) 330 #define SYNC_601 \ 331 BEGIN_FTR_SECTION \ 332 sync; \ 333 END_FTR_SECTION_IFSET(CPU_FTR_601) 334 #define ISYNC_601 \ 335 BEGIN_FTR_SECTION \ 336 isync; \ 337 END_FTR_SECTION_IFSET(CPU_FTR_601) 338 #else 339 #define SYNC 340 #define SYNC_601 341 #define ISYNC_601 342 #endif 343 344 #ifdef CONFIG_PPC_CELL 345 #define MFTB(dest) \ 346 90: mftb dest; \ 347 BEGIN_FTR_SECTION_NESTED(96); \ 348 cmpwi dest,0; \ 349 beq- 90b; \ 350 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 351 #else 352 #define MFTB(dest) mftb dest 353 #endif 354 355 #ifndef CONFIG_SMP 356 #define TLBSYNC 357 #else /* CONFIG_SMP */ 358 /* tlbsync is not implemented on 601 */ 359 #define TLBSYNC \ 360 BEGIN_FTR_SECTION \ 361 tlbsync; \ 362 sync; \ 363 END_FTR_SECTION_IFCLR(CPU_FTR_601) 364 #endif 365 366 367 /* 368 * This instruction is not implemented on the PPC 603 or 601; however, on 369 * the 403GCX and 405GP tlbia IS defined and tlbie is not. 370 * All of these instructions exist in the 8xx, they have magical powers, 371 * and they must be used. 372 */ 373 374 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx) 375 #define tlbia \ 376 li r4,1024; \ 377 mtctr r4; \ 378 lis r4,KERNELBASE@h; \ 379 0: tlbie r4; \ 380 addi r4,r4,0x1000; \ 381 bdnz 0b 382 #endif 383 384 385 #ifdef CONFIG_IBM440EP_ERR42 386 #define PPC440EP_ERR42 isync 387 #else 388 #define PPC440EP_ERR42 389 #endif 390 391 392 #if defined(CONFIG_BOOKE) 393 #define toreal(rd) 394 #define fromreal(rd) 395 396 /* 397 * We use addis to ensure compatibility with the "classic" ppc versions of 398 * these macros, which use rs = 0 to get the tophys offset in rd, rather than 399 * converting the address in r0, and so this version has to do that too 400 * (i.e. set register rd to 0 when rs == 0). 401 */ 402 #define tophys(rd,rs) \ 403 addis rd,rs,0 404 405 #define tovirt(rd,rs) \ 406 addis rd,rs,0 407 408 #elif defined(CONFIG_PPC64) 409 #define toreal(rd) /* we can access c000... in real mode */ 410 #define fromreal(rd) 411 412 #define tophys(rd,rs) \ 413 clrldi rd,rs,2 414 415 #define tovirt(rd,rs) \ 416 rotldi rd,rs,16; \ 417 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ 418 rotldi rd,rd,48 419 #else 420 /* 421 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the 422 * physical base address of RAM at compile time. 423 */ 424 #define toreal(rd) tophys(rd,rd) 425 #define fromreal(rd) tovirt(rd,rd) 426 427 #define tophys(rd,rs) \ 428 0: addis rd,rs,-PAGE_OFFSET@h; \ 429 .section ".vtop_fixup","aw"; \ 430 .align 1; \ 431 .long 0b; \ 432 .previous 433 434 #define tovirt(rd,rs) \ 435 0: addis rd,rs,PAGE_OFFSET@h; \ 436 .section ".ptov_fixup","aw"; \ 437 .align 1; \ 438 .long 0b; \ 439 .previous 440 #endif 441 442 #ifdef CONFIG_PPC64 443 #define RFI rfid 444 #define MTMSRD(r) mtmsrd r 445 446 #else 447 #define FIX_SRR1(ra, rb) 448 #ifndef CONFIG_40x 449 #define RFI rfi 450 #else 451 #define RFI rfi; b . /* Prevent prefetch past rfi */ 452 #endif 453 #define MTMSRD(r) mtmsr r 454 #define CLR_TOP32(r) 455 #endif 456 457 #endif /* __KERNEL__ */ 458 459 /* The boring bits... */ 460 461 /* Condition Register Bit Fields */ 462 463 #define cr0 0 464 #define cr1 1 465 #define cr2 2 466 #define cr3 3 467 #define cr4 4 468 #define cr5 5 469 #define cr6 6 470 #define cr7 7 471 472 473 /* General Purpose Registers (GPRs) */ 474 475 #define r0 0 476 #define r1 1 477 #define r2 2 478 #define r3 3 479 #define r4 4 480 #define r5 5 481 #define r6 6 482 #define r7 7 483 #define r8 8 484 #define r9 9 485 #define r10 10 486 #define r11 11 487 #define r12 12 488 #define r13 13 489 #define r14 14 490 #define r15 15 491 #define r16 16 492 #define r17 17 493 #define r18 18 494 #define r19 19 495 #define r20 20 496 #define r21 21 497 #define r22 22 498 #define r23 23 499 #define r24 24 500 #define r25 25 501 #define r26 26 502 #define r27 27 503 #define r28 28 504 #define r29 29 505 #define r30 30 506 #define r31 31 507 508 509 /* Floating Point Registers (FPRs) */ 510 511 #define fr0 0 512 #define fr1 1 513 #define fr2 2 514 #define fr3 3 515 #define fr4 4 516 #define fr5 5 517 #define fr6 6 518 #define fr7 7 519 #define fr8 8 520 #define fr9 9 521 #define fr10 10 522 #define fr11 11 523 #define fr12 12 524 #define fr13 13 525 #define fr14 14 526 #define fr15 15 527 #define fr16 16 528 #define fr17 17 529 #define fr18 18 530 #define fr19 19 531 #define fr20 20 532 #define fr21 21 533 #define fr22 22 534 #define fr23 23 535 #define fr24 24 536 #define fr25 25 537 #define fr26 26 538 #define fr27 27 539 #define fr28 28 540 #define fr29 29 541 #define fr30 30 542 #define fr31 31 543 544 /* AltiVec Registers (VPRs) */ 545 546 #define vr0 0 547 #define vr1 1 548 #define vr2 2 549 #define vr3 3 550 #define vr4 4 551 #define vr5 5 552 #define vr6 6 553 #define vr7 7 554 #define vr8 8 555 #define vr9 9 556 #define vr10 10 557 #define vr11 11 558 #define vr12 12 559 #define vr13 13 560 #define vr14 14 561 #define vr15 15 562 #define vr16 16 563 #define vr17 17 564 #define vr18 18 565 #define vr19 19 566 #define vr20 20 567 #define vr21 21 568 #define vr22 22 569 #define vr23 23 570 #define vr24 24 571 #define vr25 25 572 #define vr26 26 573 #define vr27 27 574 #define vr28 28 575 #define vr29 29 576 #define vr30 30 577 #define vr31 31 578 579 /* VSX Registers (VSRs) */ 580 581 #define vsr0 0 582 #define vsr1 1 583 #define vsr2 2 584 #define vsr3 3 585 #define vsr4 4 586 #define vsr5 5 587 #define vsr6 6 588 #define vsr7 7 589 #define vsr8 8 590 #define vsr9 9 591 #define vsr10 10 592 #define vsr11 11 593 #define vsr12 12 594 #define vsr13 13 595 #define vsr14 14 596 #define vsr15 15 597 #define vsr16 16 598 #define vsr17 17 599 #define vsr18 18 600 #define vsr19 19 601 #define vsr20 20 602 #define vsr21 21 603 #define vsr22 22 604 #define vsr23 23 605 #define vsr24 24 606 #define vsr25 25 607 #define vsr26 26 608 #define vsr27 27 609 #define vsr28 28 610 #define vsr29 29 611 #define vsr30 30 612 #define vsr31 31 613 #define vsr32 32 614 #define vsr33 33 615 #define vsr34 34 616 #define vsr35 35 617 #define vsr36 36 618 #define vsr37 37 619 #define vsr38 38 620 #define vsr39 39 621 #define vsr40 40 622 #define vsr41 41 623 #define vsr42 42 624 #define vsr43 43 625 #define vsr44 44 626 #define vsr45 45 627 #define vsr46 46 628 #define vsr47 47 629 #define vsr48 48 630 #define vsr49 49 631 #define vsr50 50 632 #define vsr51 51 633 #define vsr52 52 634 #define vsr53 53 635 #define vsr54 54 636 #define vsr55 55 637 #define vsr56 56 638 #define vsr57 57 639 #define vsr58 58 640 #define vsr59 59 641 #define vsr60 60 642 #define vsr61 61 643 #define vsr62 62 644 #define vsr63 63 645 646 /* SPE Registers (EVPRs) */ 647 648 #define evr0 0 649 #define evr1 1 650 #define evr2 2 651 #define evr3 3 652 #define evr4 4 653 #define evr5 5 654 #define evr6 6 655 #define evr7 7 656 #define evr8 8 657 #define evr9 9 658 #define evr10 10 659 #define evr11 11 660 #define evr12 12 661 #define evr13 13 662 #define evr14 14 663 #define evr15 15 664 #define evr16 16 665 #define evr17 17 666 #define evr18 18 667 #define evr19 19 668 #define evr20 20 669 #define evr21 21 670 #define evr22 22 671 #define evr23 23 672 #define evr24 24 673 #define evr25 25 674 #define evr26 26 675 #define evr27 27 676 #define evr28 28 677 #define evr29 29 678 #define evr30 30 679 #define evr31 31 680 681 /* some stab codes */ 682 #define N_FUN 36 683 #define N_RSYM 64 684 #define N_SLINE 68 685 #define N_SO 100 686 687 #endif /* __ASSEMBLY__ */ 688 689 #endif /* _ASM_POWERPC_PPC_ASM_H */ 690