1 /*
2 * linux/arch/arm/mach-sa1100/cpu-sa1110.c
3 *
4 * Copyright (C) 2001 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Note: there are two erratas that apply to the SA1110 here:
11 * 7 - SDRAM auto-power-up failure (rev A0)
12 * 13 - Corruption of internal register reads/writes following
13 * SDRAM reads (rev A0, B0, B1)
14 *
15 * We ignore rev. A0 and B0 devices; I don't think they're worth supporting.
16 *
17 * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
18 */
19 #include <linux/moduleparam.h>
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/sched.h>
23 #include <linux/cpufreq.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/io.h>
27
28 #include <mach/hardware.h>
29 #include <asm/cputype.h>
30 #include <asm/mach-types.h>
31 #include <asm/system.h>
32
33 #include "generic.h"
34
35 #undef DEBUG
36
37 static struct cpufreq_driver sa1110_driver;
38
39 struct sdram_params {
40 const char name[16];
41 u_char rows; /* bits */
42 u_char cas_latency; /* cycles */
43 u_char tck; /* clock cycle time (ns) */
44 u_char trcd; /* activate to r/w (ns) */
45 u_char trp; /* precharge to activate (ns) */
46 u_char twr; /* write recovery time (ns) */
47 u_short refresh; /* refresh time for array (us) */
48 };
49
50 struct sdram_info {
51 u_int mdcnfg;
52 u_int mdrefr;
53 u_int mdcas[3];
54 };
55
56 static struct sdram_params sdram_tbl[] __initdata = {
57 { /* Toshiba TC59SM716 CL2 */
58 .name = "TC59SM716-CL2",
59 .rows = 12,
60 .tck = 10,
61 .trcd = 20,
62 .trp = 20,
63 .twr = 10,
64 .refresh = 64000,
65 .cas_latency = 2,
66 }, { /* Toshiba TC59SM716 CL3 */
67 .name = "TC59SM716-CL3",
68 .rows = 12,
69 .tck = 8,
70 .trcd = 20,
71 .trp = 20,
72 .twr = 8,
73 .refresh = 64000,
74 .cas_latency = 3,
75 }, { /* Samsung K4S641632D TC75 */
76 .name = "K4S641632D",
77 .rows = 14,
78 .tck = 9,
79 .trcd = 27,
80 .trp = 20,
81 .twr = 9,
82 .refresh = 64000,
83 .cas_latency = 3,
84 }, { /* Samsung K4S281632B-1H */
85 .name = "K4S281632B-1H",
86 .rows = 12,
87 .tck = 10,
88 .trp = 20,
89 .twr = 10,
90 .refresh = 64000,
91 .cas_latency = 3,
92 }, { /* Samsung KM416S4030CT */
93 .name = "KM416S4030CT",
94 .rows = 13,
95 .tck = 8,
96 .trcd = 24, /* 3 CLKs */
97 .trp = 24, /* 3 CLKs */
98 .twr = 16, /* Trdl: 2 CLKs */
99 .refresh = 64000,
100 .cas_latency = 3,
101 }, { /* Winbond W982516AH75L CL3 */
102 .name = "W982516AH75L",
103 .rows = 16,
104 .tck = 8,
105 .trcd = 20,
106 .trp = 20,
107 .twr = 8,
108 .refresh = 64000,
109 .cas_latency = 3,
110 },
111 };
112
113 static struct sdram_params sdram_params;
114
115 /*
116 * Given a period in ns and frequency in khz, calculate the number of
117 * cycles of frequency in period. Note that we round up to the next
118 * cycle, even if we are only slightly over.
119 */
ns_to_cycles(u_int ns,u_int khz)120 static inline u_int ns_to_cycles(u_int ns, u_int khz)
121 {
122 return (ns * khz + 999999) / 1000000;
123 }
124
125 /*
126 * Create the MDCAS register bit pattern.
127 */
set_mdcas(u_int * mdcas,int delayed,u_int rcd)128 static inline void set_mdcas(u_int *mdcas, int delayed, u_int rcd)
129 {
130 u_int shift;
131
132 rcd = 2 * rcd - 1;
133 shift = delayed + 1 + rcd;
134
135 mdcas[0] = (1 << rcd) - 1;
136 mdcas[0] |= 0x55555555 << shift;
137 mdcas[1] = mdcas[2] = 0x55555555 << (shift & 1);
138 }
139
140 static void
sdram_calculate_timing(struct sdram_info * sd,u_int cpu_khz,struct sdram_params * sdram)141 sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz,
142 struct sdram_params *sdram)
143 {
144 u_int mem_khz, sd_khz, trp, twr;
145
146 mem_khz = cpu_khz / 2;
147 sd_khz = mem_khz;
148
149 /*
150 * If SDCLK would invalidate the SDRAM timings,
151 * run SDCLK at half speed.
152 *
153 * CPU steppings prior to B2 must either run the memory at
154 * half speed or use delayed read latching (errata 13).
155 */
156 if ((ns_to_cycles(sdram->tck, sd_khz) > 1) ||
157 (CPU_REVISION < CPU_SA1110_B2 && sd_khz < 62000))
158 sd_khz /= 2;
159
160 sd->mdcnfg = MDCNFG & 0x007f007f;
161
162 twr = ns_to_cycles(sdram->twr, mem_khz);
163
164 /* trp should always be >1 */
165 trp = ns_to_cycles(sdram->trp, mem_khz) - 1;
166 if (trp < 1)
167 trp = 1;
168
169 sd->mdcnfg |= trp << 8;
170 sd->mdcnfg |= trp << 24;
171 sd->mdcnfg |= sdram->cas_latency << 12;
172 sd->mdcnfg |= sdram->cas_latency << 28;
173 sd->mdcnfg |= twr << 14;
174 sd->mdcnfg |= twr << 30;
175
176 sd->mdrefr = MDREFR & 0xffbffff0;
177 sd->mdrefr |= 7;
178
179 if (sd_khz != mem_khz)
180 sd->mdrefr |= MDREFR_K1DB2;
181
182 /* initial number of '1's in MDCAS + 1 */
183 set_mdcas(sd->mdcas, sd_khz >= 62000, ns_to_cycles(sdram->trcd, mem_khz));
184
185 #ifdef DEBUG
186 printk("MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
187 sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1], sd->mdcas[2]);
188 #endif
189 }
190
191 /*
192 * Set the SDRAM refresh rate.
193 */
sdram_set_refresh(u_int dri)194 static inline void sdram_set_refresh(u_int dri)
195 {
196 MDREFR = (MDREFR & 0xffff000f) | (dri << 4);
197 (void) MDREFR;
198 }
199
200 /*
201 * Update the refresh period. We do this such that we always refresh
202 * the SDRAMs within their permissible period. The refresh period is
203 * always a multiple of the memory clock (fixed at cpu_clock / 2).
204 *
205 * FIXME: we don't currently take account of burst accesses here,
206 * but neither do Intels DM nor Angel.
207 */
208 static void
sdram_update_refresh(u_int cpu_khz,struct sdram_params * sdram)209 sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram)
210 {
211 u_int ns_row = (sdram->refresh * 1000) >> sdram->rows;
212 u_int dri = ns_to_cycles(ns_row, cpu_khz / 2) / 32;
213
214 #ifdef DEBUG
215 mdelay(250);
216 printk("new dri value = %d\n", dri);
217 #endif
218
219 sdram_set_refresh(dri);
220 }
221
222 /*
223 * Ok, set the CPU frequency.
224 */
sa1110_target(struct cpufreq_policy * policy,unsigned int target_freq,unsigned int relation)225 static int sa1110_target(struct cpufreq_policy *policy,
226 unsigned int target_freq,
227 unsigned int relation)
228 {
229 struct sdram_params *sdram = &sdram_params;
230 struct cpufreq_freqs freqs;
231 struct sdram_info sd;
232 unsigned long flags;
233 unsigned int ppcr, unused;
234
235 switch(relation){
236 case CPUFREQ_RELATION_L:
237 ppcr = sa11x0_freq_to_ppcr(target_freq);
238 if (sa11x0_ppcr_to_freq(ppcr) > policy->max)
239 ppcr--;
240 break;
241 case CPUFREQ_RELATION_H:
242 ppcr = sa11x0_freq_to_ppcr(target_freq);
243 if (ppcr && (sa11x0_ppcr_to_freq(ppcr) > target_freq) &&
244 (sa11x0_ppcr_to_freq(ppcr-1) >= policy->min))
245 ppcr--;
246 break;
247 default:
248 return -EINVAL;
249 }
250
251 freqs.old = sa11x0_getspeed(0);
252 freqs.new = sa11x0_ppcr_to_freq(ppcr);
253 freqs.cpu = 0;
254
255 sdram_calculate_timing(&sd, freqs.new, sdram);
256
257 #if 0
258 /*
259 * These values are wrong according to the SA1110 documentation
260 * and errata, but they seem to work. Need to get a storage
261 * scope on to the SDRAM signals to work out why.
262 */
263 if (policy->max < 147500) {
264 sd.mdrefr |= MDREFR_K1DB2;
265 sd.mdcas[0] = 0xaaaaaa7f;
266 } else {
267 sd.mdrefr &= ~MDREFR_K1DB2;
268 sd.mdcas[0] = 0xaaaaaa9f;
269 }
270 sd.mdcas[1] = 0xaaaaaaaa;
271 sd.mdcas[2] = 0xaaaaaaaa;
272 #endif
273
274 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
275
276 /*
277 * The clock could be going away for some time. Set the SDRAMs
278 * to refresh rapidly (every 64 memory clock cycles). To get
279 * through the whole array, we need to wait 262144 mclk cycles.
280 * We wait 20ms to be safe.
281 */
282 sdram_set_refresh(2);
283 if (!irqs_disabled()) {
284 msleep(20);
285 } else {
286 mdelay(20);
287 }
288
289 /*
290 * Reprogram the DRAM timings with interrupts disabled, and
291 * ensure that we are doing this within a complete cache line.
292 * This means that we won't access SDRAM for the duration of
293 * the programming.
294 */
295 local_irq_save(flags);
296 asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
297 udelay(10);
298 __asm__ __volatile__(" \n\
299 b 2f \n\
300 .align 5 \n\
301 1: str %3, [%1, #0] @ MDCNFG \n\
302 str %4, [%1, #28] @ MDREFR \n\
303 str %5, [%1, #4] @ MDCAS0 \n\
304 str %6, [%1, #8] @ MDCAS1 \n\
305 str %7, [%1, #12] @ MDCAS2 \n\
306 str %8, [%2, #0] @ PPCR \n\
307 ldr %0, [%1, #0] \n\
308 b 3f \n\
309 2: b 1b \n\
310 3: nop \n\
311 nop"
312 : "=&r" (unused)
313 : "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg),
314 "r" (sd.mdrefr), "r" (sd.mdcas[0]),
315 "r" (sd.mdcas[1]), "r" (sd.mdcas[2]), "r" (ppcr));
316 local_irq_restore(flags);
317
318 /*
319 * Now, return the SDRAM refresh back to normal.
320 */
321 sdram_update_refresh(freqs.new, sdram);
322
323 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
324
325 return 0;
326 }
327
sa1110_cpu_init(struct cpufreq_policy * policy)328 static int __init sa1110_cpu_init(struct cpufreq_policy *policy)
329 {
330 if (policy->cpu != 0)
331 return -EINVAL;
332 policy->cur = policy->min = policy->max = sa11x0_getspeed(0);
333 policy->cpuinfo.min_freq = 59000;
334 policy->cpuinfo.max_freq = 287000;
335 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
336 return 0;
337 }
338
339 static struct cpufreq_driver sa1110_driver = {
340 .flags = CPUFREQ_STICKY,
341 .verify = sa11x0_verify_speed,
342 .target = sa1110_target,
343 .get = sa11x0_getspeed,
344 .init = sa1110_cpu_init,
345 .name = "sa1110",
346 };
347
sa1110_find_sdram(const char * name)348 static struct sdram_params *sa1110_find_sdram(const char *name)
349 {
350 struct sdram_params *sdram;
351
352 for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl); sdram++)
353 if (strcmp(name, sdram->name) == 0)
354 return sdram;
355
356 return NULL;
357 }
358
359 static char sdram_name[16];
360
sa1110_clk_init(void)361 static int __init sa1110_clk_init(void)
362 {
363 struct sdram_params *sdram;
364 const char *name = sdram_name;
365
366 if (!name[0]) {
367 if (machine_is_assabet())
368 name = "TC59SM716-CL3";
369
370 if (machine_is_pt_system3())
371 name = "K4S641632D";
372
373 if (machine_is_h3100())
374 name = "KM416S4030CT";
375 if (machine_is_jornada720())
376 name = "K4S281632B-1H";
377 }
378
379 sdram = sa1110_find_sdram(name);
380 if (sdram) {
381 printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d"
382 " twr: %d refresh: %d cas_latency: %d\n",
383 sdram->tck, sdram->trcd, sdram->trp,
384 sdram->twr, sdram->refresh, sdram->cas_latency);
385
386 memcpy(&sdram_params, sdram, sizeof(sdram_params));
387
388 return cpufreq_register_driver(&sa1110_driver);
389 }
390
391 return 0;
392 }
393
394 module_param_string(sdram, sdram_name, sizeof(sdram_name), 0);
395 arch_initcall(sa1110_clk_init);
396