1 /* $Id: hscx.c,v 1.24.2.4 2004/01/24 20:47:23 keil Exp $
2 *
3 * HSCX specific routines
4 *
5 * Author Karsten Keil
6 * Copyright by Karsten Keil <keil@isdn4linux.de>
7 *
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
10 *
11 */
12
13 #include <linux/init.h>
14 #include "hisax.h"
15 #include "hscx.h"
16 #include "isac.h"
17 #include "isdnl1.h"
18 #include <linux/interrupt.h>
19
20 static char *HSCXVer[] =
21 {"A1", "?1", "A2", "?3", "A3", "V2.1", "?6", "?7",
22 "?8", "?9", "?10", "?11", "?12", "?13", "?14", "???"};
23
24 int
HscxVersion(struct IsdnCardState * cs,char * s)25 HscxVersion(struct IsdnCardState *cs, char *s)
26 {
27 int verA, verB;
28
29 verA = cs->BC_Read_Reg(cs, 0, HSCX_VSTR) & 0xf;
30 verB = cs->BC_Read_Reg(cs, 1, HSCX_VSTR) & 0xf;
31 printk(KERN_INFO "%s HSCX version A: %s B: %s\n", s,
32 HSCXVer[verA], HSCXVer[verB]);
33 if ((verA == 0) | (verA == 0xf) | (verB == 0) | (verB == 0xf))
34 return (1);
35 else
36 return (0);
37 }
38
39 void
modehscx(struct BCState * bcs,int mode,int bc)40 modehscx(struct BCState *bcs, int mode, int bc)
41 {
42 struct IsdnCardState *cs = bcs->cs;
43 int hscx = bcs->hw.hscx.hscx;
44
45 if (cs->debug & L1_DEB_HSCX)
46 debugl1(cs, "hscx %c mode %d ichan %d",
47 'A' + hscx, mode, bc);
48 bcs->mode = mode;
49 bcs->channel = bc;
50 cs->BC_Write_Reg(cs, hscx, HSCX_XAD1, 0xFF);
51 cs->BC_Write_Reg(cs, hscx, HSCX_XAD2, 0xFF);
52 cs->BC_Write_Reg(cs, hscx, HSCX_RAH2, 0xFF);
53 cs->BC_Write_Reg(cs, hscx, HSCX_XBCH, 0x0);
54 cs->BC_Write_Reg(cs, hscx, HSCX_RLCR, 0x0);
55 cs->BC_Write_Reg(cs, hscx, HSCX_CCR1,
56 test_bit(HW_IPAC, &cs->HW_Flags) ? 0x82 : 0x85);
57 cs->BC_Write_Reg(cs, hscx, HSCX_CCR2, 0x30);
58 cs->BC_Write_Reg(cs, hscx, HSCX_XCCR, 7);
59 cs->BC_Write_Reg(cs, hscx, HSCX_RCCR, 7);
60
61 /* Switch IOM 1 SSI */
62 if (test_bit(HW_IOM1, &cs->HW_Flags) && (hscx == 0))
63 bc = 1 - bc;
64
65 if (bc == 0) {
66 cs->BC_Write_Reg(cs, hscx, HSCX_TSAX,
67 test_bit(HW_IOM1, &cs->HW_Flags) ? 0x7 : bcs->hw.hscx.tsaxr0);
68 cs->BC_Write_Reg(cs, hscx, HSCX_TSAR,
69 test_bit(HW_IOM1, &cs->HW_Flags) ? 0x7 : bcs->hw.hscx.tsaxr0);
70 } else {
71 cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, bcs->hw.hscx.tsaxr1);
72 cs->BC_Write_Reg(cs, hscx, HSCX_TSAR, bcs->hw.hscx.tsaxr1);
73 }
74 switch (mode) {
75 case (L1_MODE_NULL):
76 cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, 0x1f);
77 cs->BC_Write_Reg(cs, hscx, HSCX_TSAR, 0x1f);
78 cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0x84);
79 break;
80 case (L1_MODE_TRANS):
81 cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0xe4);
82 break;
83 case (L1_MODE_HDLC):
84 cs->BC_Write_Reg(cs, hscx, HSCX_CCR1,
85 test_bit(HW_IPAC, &cs->HW_Flags) ? 0x8a : 0x8d);
86 cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0x8c);
87 break;
88 }
89 if (mode)
90 cs->BC_Write_Reg(cs, hscx, HSCX_CMDR, 0x41);
91 cs->BC_Write_Reg(cs, hscx, HSCX_ISTA, 0x00);
92 }
93
94 void
hscx_l2l1(struct PStack * st,int pr,void * arg)95 hscx_l2l1(struct PStack *st, int pr, void *arg)
96 {
97 struct BCState *bcs = st->l1.bcs;
98 u_long flags;
99 struct sk_buff *skb = arg;
100
101 switch (pr) {
102 case (PH_DATA | REQUEST):
103 spin_lock_irqsave(&bcs->cs->lock, flags);
104 if (bcs->tx_skb) {
105 skb_queue_tail(&bcs->squeue, skb);
106 } else {
107 bcs->tx_skb = skb;
108 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
109 bcs->hw.hscx.count = 0;
110 bcs->cs->BC_Send_Data(bcs);
111 }
112 spin_unlock_irqrestore(&bcs->cs->lock, flags);
113 break;
114 case (PH_PULL | INDICATION):
115 spin_lock_irqsave(&bcs->cs->lock, flags);
116 if (bcs->tx_skb) {
117 printk(KERN_WARNING "hscx_l2l1: this shouldn't happen\n");
118 } else {
119 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
120 bcs->tx_skb = skb;
121 bcs->hw.hscx.count = 0;
122 bcs->cs->BC_Send_Data(bcs);
123 }
124 spin_unlock_irqrestore(&bcs->cs->lock, flags);
125 break;
126 case (PH_PULL | REQUEST):
127 if (!bcs->tx_skb) {
128 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
129 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
130 } else
131 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
132 break;
133 case (PH_ACTIVATE | REQUEST):
134 spin_lock_irqsave(&bcs->cs->lock, flags);
135 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
136 modehscx(bcs, st->l1.mode, st->l1.bc);
137 spin_unlock_irqrestore(&bcs->cs->lock, flags);
138 l1_msg_b(st, pr, arg);
139 break;
140 case (PH_DEACTIVATE | REQUEST):
141 l1_msg_b(st, pr, arg);
142 break;
143 case (PH_DEACTIVATE | CONFIRM):
144 spin_lock_irqsave(&bcs->cs->lock, flags);
145 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
146 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
147 modehscx(bcs, 0, st->l1.bc);
148 spin_unlock_irqrestore(&bcs->cs->lock, flags);
149 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
150 break;
151 }
152 }
153
154 static void
close_hscxstate(struct BCState * bcs)155 close_hscxstate(struct BCState *bcs)
156 {
157 modehscx(bcs, 0, bcs->channel);
158 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
159 kfree(bcs->hw.hscx.rcvbuf);
160 bcs->hw.hscx.rcvbuf = NULL;
161 kfree(bcs->blog);
162 bcs->blog = NULL;
163 skb_queue_purge(&bcs->rqueue);
164 skb_queue_purge(&bcs->squeue);
165 if (bcs->tx_skb) {
166 dev_kfree_skb_any(bcs->tx_skb);
167 bcs->tx_skb = NULL;
168 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
169 }
170 }
171 }
172
173 int
open_hscxstate(struct IsdnCardState * cs,struct BCState * bcs)174 open_hscxstate(struct IsdnCardState *cs, struct BCState *bcs)
175 {
176 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
177 if (!(bcs->hw.hscx.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
178 printk(KERN_WARNING
179 "HiSax: No memory for hscx.rcvbuf\n");
180 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
181 return (1);
182 }
183 if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
184 printk(KERN_WARNING
185 "HiSax: No memory for bcs->blog\n");
186 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
187 kfree(bcs->hw.hscx.rcvbuf);
188 bcs->hw.hscx.rcvbuf = NULL;
189 return (2);
190 }
191 skb_queue_head_init(&bcs->rqueue);
192 skb_queue_head_init(&bcs->squeue);
193 }
194 bcs->tx_skb = NULL;
195 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
196 bcs->event = 0;
197 bcs->hw.hscx.rcvidx = 0;
198 bcs->tx_cnt = 0;
199 return (0);
200 }
201
202 static int
setstack_hscx(struct PStack * st,struct BCState * bcs)203 setstack_hscx(struct PStack *st, struct BCState *bcs)
204 {
205 bcs->channel = st->l1.bc;
206 if (open_hscxstate(st->l1.hardware, bcs))
207 return (-1);
208 st->l1.bcs = bcs;
209 st->l2.l2l1 = hscx_l2l1;
210 setstack_manager(st);
211 bcs->st = st;
212 setstack_l1_B(st);
213 return (0);
214 }
215
216 void
clear_pending_hscx_ints(struct IsdnCardState * cs)217 clear_pending_hscx_ints(struct IsdnCardState *cs)
218 {
219 int val, eval;
220
221 val = cs->BC_Read_Reg(cs, 1, HSCX_ISTA);
222 debugl1(cs, "HSCX B ISTA %x", val);
223 if (val & 0x01) {
224 eval = cs->BC_Read_Reg(cs, 1, HSCX_EXIR);
225 debugl1(cs, "HSCX B EXIR %x", eval);
226 }
227 if (val & 0x02) {
228 eval = cs->BC_Read_Reg(cs, 0, HSCX_EXIR);
229 debugl1(cs, "HSCX A EXIR %x", eval);
230 }
231 val = cs->BC_Read_Reg(cs, 0, HSCX_ISTA);
232 debugl1(cs, "HSCX A ISTA %x", val);
233 val = cs->BC_Read_Reg(cs, 1, HSCX_STAR);
234 debugl1(cs, "HSCX B STAR %x", val);
235 val = cs->BC_Read_Reg(cs, 0, HSCX_STAR);
236 debugl1(cs, "HSCX A STAR %x", val);
237 /* disable all IRQ */
238 cs->BC_Write_Reg(cs, 0, HSCX_MASK, 0xFF);
239 cs->BC_Write_Reg(cs, 1, HSCX_MASK, 0xFF);
240 }
241
242 void
inithscx(struct IsdnCardState * cs)243 inithscx(struct IsdnCardState *cs)
244 {
245 cs->bcs[0].BC_SetStack = setstack_hscx;
246 cs->bcs[1].BC_SetStack = setstack_hscx;
247 cs->bcs[0].BC_Close = close_hscxstate;
248 cs->bcs[1].BC_Close = close_hscxstate;
249 cs->bcs[0].hw.hscx.hscx = 0;
250 cs->bcs[1].hw.hscx.hscx = 1;
251 cs->bcs[0].hw.hscx.tsaxr0 = 0x2f;
252 cs->bcs[0].hw.hscx.tsaxr1 = 3;
253 cs->bcs[1].hw.hscx.tsaxr0 = 0x2f;
254 cs->bcs[1].hw.hscx.tsaxr1 = 3;
255 modehscx(cs->bcs, 0, 0);
256 modehscx(cs->bcs + 1, 0, 0);
257 }
258
259 void
inithscxisac(struct IsdnCardState * cs,int part)260 inithscxisac(struct IsdnCardState *cs, int part)
261 {
262 if (part & 1) {
263 clear_pending_isac_ints(cs);
264 clear_pending_hscx_ints(cs);
265 initisac(cs);
266 inithscx(cs);
267 }
268 if (part & 2) {
269 /* Reenable all IRQ */
270 cs->writeisac(cs, ISAC_MASK, 0);
271 cs->BC_Write_Reg(cs, 0, HSCX_MASK, 0);
272 cs->BC_Write_Reg(cs, 1, HSCX_MASK, 0);
273 /* RESET Receiver and Transmitter */
274 cs->writeisac(cs, ISAC_CMDR, 0x41);
275 }
276 }
277