1 #ifndef __mmu_defs_asm_h 2 #define __mmu_defs_asm_h 3 4 /* 5 * This file is autogenerated from 6 * file: ../../inst/mmu/doc/mmu_regs.r 7 * id: mmu_regs.r,v 1.12 2004/05/06 13:48:45 mikaeln Exp 8 * last modfied: Mon Apr 11 17:03:20 2005 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/mmu_defs_asm.h ../../inst/mmu/doc/mmu_regs.r 11 * id: $Id: mmu_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16 17 #ifndef REG_FIELD 18 #define REG_FIELD( scope, reg, field, value ) \ 19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 20 #define REG_FIELD_X_( value, shift ) ((value) << shift) 21 #endif 22 23 #ifndef REG_STATE 24 #define REG_STATE( scope, reg, field, symbolic_value ) \ 25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 26 #define REG_STATE_X_( k, shift ) (k << shift) 27 #endif 28 29 #ifndef REG_MASK 30 #define REG_MASK( scope, reg, field ) \ 31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 32 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 33 #endif 34 35 #ifndef REG_LSB 36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 37 #endif 38 39 #ifndef REG_BIT 40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 41 #endif 42 43 #ifndef REG_ADDR 44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) 46 #endif 47 48 #ifndef REG_ADDR_VECT 49 #define REG_ADDR_VECT( scope, inst, reg, index ) \ 50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 51 STRIDE_##scope##_##reg ) 52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 53 ((inst) + offs + (index) * stride) 54 #endif 55 56 /* Register rw_mm_cfg, scope mmu, type rw */ 57 #define reg_mmu_rw_mm_cfg___seg_0___lsb 0 58 #define reg_mmu_rw_mm_cfg___seg_0___width 1 59 #define reg_mmu_rw_mm_cfg___seg_0___bit 0 60 #define reg_mmu_rw_mm_cfg___seg_1___lsb 1 61 #define reg_mmu_rw_mm_cfg___seg_1___width 1 62 #define reg_mmu_rw_mm_cfg___seg_1___bit 1 63 #define reg_mmu_rw_mm_cfg___seg_2___lsb 2 64 #define reg_mmu_rw_mm_cfg___seg_2___width 1 65 #define reg_mmu_rw_mm_cfg___seg_2___bit 2 66 #define reg_mmu_rw_mm_cfg___seg_3___lsb 3 67 #define reg_mmu_rw_mm_cfg___seg_3___width 1 68 #define reg_mmu_rw_mm_cfg___seg_3___bit 3 69 #define reg_mmu_rw_mm_cfg___seg_4___lsb 4 70 #define reg_mmu_rw_mm_cfg___seg_4___width 1 71 #define reg_mmu_rw_mm_cfg___seg_4___bit 4 72 #define reg_mmu_rw_mm_cfg___seg_5___lsb 5 73 #define reg_mmu_rw_mm_cfg___seg_5___width 1 74 #define reg_mmu_rw_mm_cfg___seg_5___bit 5 75 #define reg_mmu_rw_mm_cfg___seg_6___lsb 6 76 #define reg_mmu_rw_mm_cfg___seg_6___width 1 77 #define reg_mmu_rw_mm_cfg___seg_6___bit 6 78 #define reg_mmu_rw_mm_cfg___seg_7___lsb 7 79 #define reg_mmu_rw_mm_cfg___seg_7___width 1 80 #define reg_mmu_rw_mm_cfg___seg_7___bit 7 81 #define reg_mmu_rw_mm_cfg___seg_8___lsb 8 82 #define reg_mmu_rw_mm_cfg___seg_8___width 1 83 #define reg_mmu_rw_mm_cfg___seg_8___bit 8 84 #define reg_mmu_rw_mm_cfg___seg_9___lsb 9 85 #define reg_mmu_rw_mm_cfg___seg_9___width 1 86 #define reg_mmu_rw_mm_cfg___seg_9___bit 9 87 #define reg_mmu_rw_mm_cfg___seg_a___lsb 10 88 #define reg_mmu_rw_mm_cfg___seg_a___width 1 89 #define reg_mmu_rw_mm_cfg___seg_a___bit 10 90 #define reg_mmu_rw_mm_cfg___seg_b___lsb 11 91 #define reg_mmu_rw_mm_cfg___seg_b___width 1 92 #define reg_mmu_rw_mm_cfg___seg_b___bit 11 93 #define reg_mmu_rw_mm_cfg___seg_c___lsb 12 94 #define reg_mmu_rw_mm_cfg___seg_c___width 1 95 #define reg_mmu_rw_mm_cfg___seg_c___bit 12 96 #define reg_mmu_rw_mm_cfg___seg_d___lsb 13 97 #define reg_mmu_rw_mm_cfg___seg_d___width 1 98 #define reg_mmu_rw_mm_cfg___seg_d___bit 13 99 #define reg_mmu_rw_mm_cfg___seg_e___lsb 14 100 #define reg_mmu_rw_mm_cfg___seg_e___width 1 101 #define reg_mmu_rw_mm_cfg___seg_e___bit 14 102 #define reg_mmu_rw_mm_cfg___seg_f___lsb 15 103 #define reg_mmu_rw_mm_cfg___seg_f___width 1 104 #define reg_mmu_rw_mm_cfg___seg_f___bit 15 105 #define reg_mmu_rw_mm_cfg___inv___lsb 16 106 #define reg_mmu_rw_mm_cfg___inv___width 1 107 #define reg_mmu_rw_mm_cfg___inv___bit 16 108 #define reg_mmu_rw_mm_cfg___ex___lsb 17 109 #define reg_mmu_rw_mm_cfg___ex___width 1 110 #define reg_mmu_rw_mm_cfg___ex___bit 17 111 #define reg_mmu_rw_mm_cfg___acc___lsb 18 112 #define reg_mmu_rw_mm_cfg___acc___width 1 113 #define reg_mmu_rw_mm_cfg___acc___bit 18 114 #define reg_mmu_rw_mm_cfg___we___lsb 19 115 #define reg_mmu_rw_mm_cfg___we___width 1 116 #define reg_mmu_rw_mm_cfg___we___bit 19 117 #define reg_mmu_rw_mm_cfg_offset 0 118 119 /* Register rw_mm_kbase_lo, scope mmu, type rw */ 120 #define reg_mmu_rw_mm_kbase_lo___base_0___lsb 0 121 #define reg_mmu_rw_mm_kbase_lo___base_0___width 4 122 #define reg_mmu_rw_mm_kbase_lo___base_1___lsb 4 123 #define reg_mmu_rw_mm_kbase_lo___base_1___width 4 124 #define reg_mmu_rw_mm_kbase_lo___base_2___lsb 8 125 #define reg_mmu_rw_mm_kbase_lo___base_2___width 4 126 #define reg_mmu_rw_mm_kbase_lo___base_3___lsb 12 127 #define reg_mmu_rw_mm_kbase_lo___base_3___width 4 128 #define reg_mmu_rw_mm_kbase_lo___base_4___lsb 16 129 #define reg_mmu_rw_mm_kbase_lo___base_4___width 4 130 #define reg_mmu_rw_mm_kbase_lo___base_5___lsb 20 131 #define reg_mmu_rw_mm_kbase_lo___base_5___width 4 132 #define reg_mmu_rw_mm_kbase_lo___base_6___lsb 24 133 #define reg_mmu_rw_mm_kbase_lo___base_6___width 4 134 #define reg_mmu_rw_mm_kbase_lo___base_7___lsb 28 135 #define reg_mmu_rw_mm_kbase_lo___base_7___width 4 136 #define reg_mmu_rw_mm_kbase_lo_offset 4 137 138 /* Register rw_mm_kbase_hi, scope mmu, type rw */ 139 #define reg_mmu_rw_mm_kbase_hi___base_8___lsb 0 140 #define reg_mmu_rw_mm_kbase_hi___base_8___width 4 141 #define reg_mmu_rw_mm_kbase_hi___base_9___lsb 4 142 #define reg_mmu_rw_mm_kbase_hi___base_9___width 4 143 #define reg_mmu_rw_mm_kbase_hi___base_a___lsb 8 144 #define reg_mmu_rw_mm_kbase_hi___base_a___width 4 145 #define reg_mmu_rw_mm_kbase_hi___base_b___lsb 12 146 #define reg_mmu_rw_mm_kbase_hi___base_b___width 4 147 #define reg_mmu_rw_mm_kbase_hi___base_c___lsb 16 148 #define reg_mmu_rw_mm_kbase_hi___base_c___width 4 149 #define reg_mmu_rw_mm_kbase_hi___base_d___lsb 20 150 #define reg_mmu_rw_mm_kbase_hi___base_d___width 4 151 #define reg_mmu_rw_mm_kbase_hi___base_e___lsb 24 152 #define reg_mmu_rw_mm_kbase_hi___base_e___width 4 153 #define reg_mmu_rw_mm_kbase_hi___base_f___lsb 28 154 #define reg_mmu_rw_mm_kbase_hi___base_f___width 4 155 #define reg_mmu_rw_mm_kbase_hi_offset 8 156 157 /* Register r_mm_cause, scope mmu, type r */ 158 #define reg_mmu_r_mm_cause___pid___lsb 0 159 #define reg_mmu_r_mm_cause___pid___width 8 160 #define reg_mmu_r_mm_cause___op___lsb 8 161 #define reg_mmu_r_mm_cause___op___width 2 162 #define reg_mmu_r_mm_cause___vpn___lsb 13 163 #define reg_mmu_r_mm_cause___vpn___width 19 164 #define reg_mmu_r_mm_cause_offset 12 165 166 /* Register rw_mm_tlb_sel, scope mmu, type rw */ 167 #define reg_mmu_rw_mm_tlb_sel___idx___lsb 0 168 #define reg_mmu_rw_mm_tlb_sel___idx___width 4 169 #define reg_mmu_rw_mm_tlb_sel___set___lsb 4 170 #define reg_mmu_rw_mm_tlb_sel___set___width 2 171 #define reg_mmu_rw_mm_tlb_sel_offset 16 172 173 /* Register rw_mm_tlb_lo, scope mmu, type rw */ 174 #define reg_mmu_rw_mm_tlb_lo___x___lsb 0 175 #define reg_mmu_rw_mm_tlb_lo___x___width 1 176 #define reg_mmu_rw_mm_tlb_lo___x___bit 0 177 #define reg_mmu_rw_mm_tlb_lo___w___lsb 1 178 #define reg_mmu_rw_mm_tlb_lo___w___width 1 179 #define reg_mmu_rw_mm_tlb_lo___w___bit 1 180 #define reg_mmu_rw_mm_tlb_lo___k___lsb 2 181 #define reg_mmu_rw_mm_tlb_lo___k___width 1 182 #define reg_mmu_rw_mm_tlb_lo___k___bit 2 183 #define reg_mmu_rw_mm_tlb_lo___v___lsb 3 184 #define reg_mmu_rw_mm_tlb_lo___v___width 1 185 #define reg_mmu_rw_mm_tlb_lo___v___bit 3 186 #define reg_mmu_rw_mm_tlb_lo___g___lsb 4 187 #define reg_mmu_rw_mm_tlb_lo___g___width 1 188 #define reg_mmu_rw_mm_tlb_lo___g___bit 4 189 #define reg_mmu_rw_mm_tlb_lo___pfn___lsb 13 190 #define reg_mmu_rw_mm_tlb_lo___pfn___width 19 191 #define reg_mmu_rw_mm_tlb_lo_offset 20 192 193 /* Register rw_mm_tlb_hi, scope mmu, type rw */ 194 #define reg_mmu_rw_mm_tlb_hi___pid___lsb 0 195 #define reg_mmu_rw_mm_tlb_hi___pid___width 8 196 #define reg_mmu_rw_mm_tlb_hi___vpn___lsb 13 197 #define reg_mmu_rw_mm_tlb_hi___vpn___width 19 198 #define reg_mmu_rw_mm_tlb_hi_offset 24 199 200 201 /* Constants */ 202 #define regk_mmu_execute 0x00000000 203 #define regk_mmu_flush 0x00000003 204 #define regk_mmu_linear 0x00000001 205 #define regk_mmu_no 0x00000000 206 #define regk_mmu_off 0x00000000 207 #define regk_mmu_on 0x00000001 208 #define regk_mmu_page 0x00000000 209 #define regk_mmu_read 0x00000001 210 #define regk_mmu_write 0x00000002 211 #define regk_mmu_yes 0x00000001 212 #endif /* __mmu_defs_asm_h */ 213