1 /* 2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 */ 4 5 /* 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ 12 #define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ 13 14 /* Base address of PBC controller */ 15 #define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) 16 /* Offsets for the PBC Controller register */ 17 18 /* PBC Board status register offset */ 19 #define PBC_BSTAT 0x000002 20 21 /* PBC Board control register 1 set address */ 22 #define PBC_BCTRL1_SET 0x000004 23 24 /* PBC Board control register 1 clear address */ 25 #define PBC_BCTRL1_CLEAR 0x000006 26 27 /* PBC Board control register 2 set address */ 28 #define PBC_BCTRL2_SET 0x000008 29 30 /* PBC Board control register 2 clear address */ 31 #define PBC_BCTRL2_CLEAR 0x00000A 32 33 /* PBC Board control register 3 set address */ 34 #define PBC_BCTRL3_SET 0x00000C 35 36 /* PBC Board control register 3 clear address */ 37 #define PBC_BCTRL3_CLEAR 0x00000E 38 39 /* PBC Board control register 4 set address */ 40 #define PBC_BCTRL4_SET 0x000010 41 42 /* PBC Board control register 4 clear address */ 43 #define PBC_BCTRL4_CLEAR 0x000012 44 45 /* PBC Board status register 1 */ 46 #define PBC_BSTAT1 0x000014 47 48 /* PBC Board interrupt status register */ 49 #define PBC_INTSTATUS 0x000016 50 51 /* PBC Board interrupt current status register */ 52 #define PBC_INTCURR_STATUS 0x000018 53 54 /* PBC Interrupt mask register set address */ 55 #define PBC_INTMASK_SET 0x00001A 56 57 /* PBC Interrupt mask register clear address */ 58 #define PBC_INTMASK_CLEAR 0x00001C 59 60 /* External UART A */ 61 #define PBC_SC16C652_UARTA 0x010000 62 63 /* External UART B */ 64 #define PBC_SC16C652_UARTB 0x010010 65 66 /* Ethernet Controller IO base address */ 67 #define PBC_CS8900A_IOBASE 0x020000 68 69 /* Ethernet Controller Memory base address */ 70 #define PBC_CS8900A_MEMBASE 0x021000 71 72 /* Ethernet Controller DMA base address */ 73 #define PBC_CS8900A_DMABASE 0x022000 74 75 /* External chip select 0 */ 76 #define PBC_XCS0 0x040000 77 78 /* LCD Display enable */ 79 #define PBC_LCD_EN_B 0x060000 80 81 /* Code test debug enable */ 82 #define PBC_CODE_B 0x070000 83 84 /* PSRAM memory select */ 85 #define PBC_PSRAM_B 0x5000000 86 87 #define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) 88 #define PBC_INTCURR_STATUS_REG (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS) 89 #define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS) 90 #define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) 91 #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4) 92 93 #define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) 94 #define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) 95 96 #define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0) 97 #define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1) 98 #define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2) 99 #define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3) 100 #define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4) 101 #define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5) 102 #define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6) 103 #define EXPIO_INT_RES7 (MXC_EXP_IO_BASE + 7) 104 #define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8) 105 #define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9) 106 #define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) 107 #define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11) 108 #define EXPIO_INT_SYNTH_IRQ (MXC_EXP_IO_BASE + 12) 109 #define EXPIO_INT_CE_INT1 (MXC_EXP_IO_BASE + 13) 110 #define EXPIO_INT_CE_INT2 (MXC_EXP_IO_BASE + 14) 111 #define EXPIO_INT_RES15 (MXC_EXP_IO_BASE + 15) 112 113 #define MXC_MAX_EXP_IO_LINES 16 114 115 /* mandatory for CONFIG_LL_DEBUG */ 116 117 #define MXC_LL_UART_PADDR UART1_BASE_ADDR 118 #define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) 119 120 #endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ 121