1 /*
2 * madgemc.c: Driver for the Madge Smart 16/4 MC16 MCA token ring card.
3 *
4 * Written 2000 by Adam Fritzler
5 *
6 * This software may be used and distributed according to the terms
7 * of the GNU General Public License, incorporated herein by reference.
8 *
9 * This driver module supports the following cards:
10 * - Madge Smart 16/4 Ringnode MC16
11 * - Madge Smart 16/4 Ringnode MC32 (??)
12 *
13 * Maintainer(s):
14 * AF Adam Fritzler
15 *
16 * Modification History:
17 * 16-Jan-00 AF Created
18 *
19 */
20 static const char version[] = "madgemc.c: v0.91 23/01/2000 by Adam Fritzler\n";
21
22 #include <linux/module.h>
23 #include <linux/mca.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/init.h>
27 #include <linux/netdevice.h>
28 #include <linux/trdevice.h>
29
30 #include <asm/system.h>
31 #include <asm/io.h>
32 #include <asm/irq.h>
33
34 #include "tms380tr.h"
35 #include "madgemc.h" /* Madge-specific constants */
36
37 #define MADGEMC_IO_EXTENT 32
38 #define MADGEMC_SIF_OFFSET 0x08
39
40 struct card_info {
41 /*
42 * These are read from the BIA ROM.
43 */
44 unsigned int manid;
45 unsigned int cardtype;
46 unsigned int cardrev;
47 unsigned int ramsize;
48
49 /*
50 * These are read from the MCA POS registers.
51 */
52 unsigned int burstmode:2;
53 unsigned int fairness:1; /* 0 = Fair, 1 = Unfair */
54 unsigned int arblevel:4;
55 unsigned int ringspeed:2; /* 0 = 4mb, 1 = 16, 2 = Auto/none */
56 unsigned int cabletype:1; /* 0 = RJ45, 1 = DB9 */
57 };
58
59 static int madgemc_open(struct net_device *dev);
60 static int madgemc_close(struct net_device *dev);
61 static int madgemc_chipset_init(struct net_device *dev);
62 static void madgemc_read_rom(struct net_device *dev, struct card_info *card);
63 static unsigned short madgemc_setnselout_pins(struct net_device *dev);
64 static void madgemc_setcabletype(struct net_device *dev, int type);
65
66 static int madgemc_mcaproc(char *buf, int slot, void *d);
67
68 static void madgemc_setregpage(struct net_device *dev, int page);
69 static void madgemc_setsifsel(struct net_device *dev, int val);
70 static void madgemc_setint(struct net_device *dev, int val);
71
72 static irqreturn_t madgemc_interrupt(int irq, void *dev_id);
73
74 /*
75 * These work around paging, however they don't guarentee you're on the
76 * right page.
77 */
78 #define SIFREADB(reg) (inb(dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
79 #define SIFWRITEB(val, reg) (outb(val, dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
80 #define SIFREADW(reg) (inw(dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
81 #define SIFWRITEW(val, reg) (outw(val, dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
82
83 /*
84 * Read a byte-length value from the register.
85 */
madgemc_sifreadb(struct net_device * dev,unsigned short reg)86 static unsigned short madgemc_sifreadb(struct net_device *dev, unsigned short reg)
87 {
88 unsigned short ret;
89 if (reg<0x8)
90 ret = SIFREADB(reg);
91 else {
92 madgemc_setregpage(dev, 1);
93 ret = SIFREADB(reg);
94 madgemc_setregpage(dev, 0);
95 }
96 return ret;
97 }
98
99 /*
100 * Write a byte-length value to a register.
101 */
madgemc_sifwriteb(struct net_device * dev,unsigned short val,unsigned short reg)102 static void madgemc_sifwriteb(struct net_device *dev, unsigned short val, unsigned short reg)
103 {
104 if (reg<0x8)
105 SIFWRITEB(val, reg);
106 else {
107 madgemc_setregpage(dev, 1);
108 SIFWRITEB(val, reg);
109 madgemc_setregpage(dev, 0);
110 }
111 return;
112 }
113
114 /*
115 * Read a word-length value from a register
116 */
madgemc_sifreadw(struct net_device * dev,unsigned short reg)117 static unsigned short madgemc_sifreadw(struct net_device *dev, unsigned short reg)
118 {
119 unsigned short ret;
120 if (reg<0x8)
121 ret = SIFREADW(reg);
122 else {
123 madgemc_setregpage(dev, 1);
124 ret = SIFREADW(reg);
125 madgemc_setregpage(dev, 0);
126 }
127 return ret;
128 }
129
130 /*
131 * Write a word-length value to a register.
132 */
madgemc_sifwritew(struct net_device * dev,unsigned short val,unsigned short reg)133 static void madgemc_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg)
134 {
135 if (reg<0x8)
136 SIFWRITEW(val, reg);
137 else {
138 madgemc_setregpage(dev, 1);
139 SIFWRITEW(val, reg);
140 madgemc_setregpage(dev, 0);
141 }
142 return;
143 }
144
145
146
madgemc_probe(struct device * device)147 static int __devinit madgemc_probe(struct device *device)
148 {
149 static int versionprinted;
150 struct net_device *dev;
151 struct net_local *tp;
152 struct card_info *card;
153 struct mca_device *mdev = to_mca_device(device);
154 int ret = 0;
155
156 if (versionprinted++ == 0)
157 printk("%s", version);
158
159 if(mca_device_claimed(mdev))
160 return -EBUSY;
161 mca_device_set_claim(mdev, 1);
162
163 dev = alloc_trdev(sizeof(struct net_local));
164 if (!dev) {
165 printk("madgemc: unable to allocate dev space\n");
166 mca_device_set_claim(mdev, 0);
167 ret = -ENOMEM;
168 goto getout;
169 }
170
171 dev->dma = 0;
172
173 card = kmalloc(sizeof(struct card_info), GFP_KERNEL);
174 if (card==NULL) {
175 printk("madgemc: unable to allocate card struct\n");
176 ret = -ENOMEM;
177 goto getout1;
178 }
179
180 /*
181 * Parse configuration information. This all comes
182 * directly from the publicly available @002d.ADF.
183 * Get it from Madge or your local ADF library.
184 */
185
186 /*
187 * Base address
188 */
189 dev->base_addr = 0x0a20 +
190 ((mdev->pos[2] & MC16_POS2_ADDR2)?0x0400:0) +
191 ((mdev->pos[0] & MC16_POS0_ADDR1)?0x1000:0) +
192 ((mdev->pos[3] & MC16_POS3_ADDR3)?0x2000:0);
193
194 /*
195 * Interrupt line
196 */
197 switch(mdev->pos[0] >> 6) { /* upper two bits */
198 case 0x1: dev->irq = 3; break;
199 case 0x2: dev->irq = 9; break; /* IRQ 2 = IRQ 9 */
200 case 0x3: dev->irq = 10; break;
201 default: dev->irq = 0; break;
202 }
203
204 if (dev->irq == 0) {
205 printk("%s: invalid IRQ\n", dev->name);
206 ret = -EBUSY;
207 goto getout2;
208 }
209
210 if (!request_region(dev->base_addr, MADGEMC_IO_EXTENT,
211 "madgemc")) {
212 printk(KERN_INFO "madgemc: unable to setup Smart MC in slot %d because of I/O base conflict at 0x%04lx\n", mdev->slot, dev->base_addr);
213 dev->base_addr += MADGEMC_SIF_OFFSET;
214 ret = -EBUSY;
215 goto getout2;
216 }
217 dev->base_addr += MADGEMC_SIF_OFFSET;
218
219 /*
220 * Arbitration Level
221 */
222 card->arblevel = ((mdev->pos[0] >> 1) & 0x7) + 8;
223
224 /*
225 * Burst mode and Fairness
226 */
227 card->burstmode = ((mdev->pos[2] >> 6) & 0x3);
228 card->fairness = ((mdev->pos[2] >> 4) & 0x1);
229
230 /*
231 * Ring Speed
232 */
233 if ((mdev->pos[1] >> 2)&0x1)
234 card->ringspeed = 2; /* not selected */
235 else if ((mdev->pos[2] >> 5) & 0x1)
236 card->ringspeed = 1; /* 16Mb */
237 else
238 card->ringspeed = 0; /* 4Mb */
239
240 /*
241 * Cable type
242 */
243 if ((mdev->pos[1] >> 6)&0x1)
244 card->cabletype = 1; /* STP/DB9 */
245 else
246 card->cabletype = 0; /* UTP/RJ-45 */
247
248
249 /*
250 * ROM Info. This requires us to actually twiddle
251 * bits on the card, so we must ensure above that
252 * the base address is free of conflict (request_region above).
253 */
254 madgemc_read_rom(dev, card);
255
256 if (card->manid != 0x4d) { /* something went wrong */
257 printk(KERN_INFO "%s: Madge MC ROM read failed (unknown manufacturer ID %02x)\n", dev->name, card->manid);
258 goto getout3;
259 }
260
261 if ((card->cardtype != 0x08) && (card->cardtype != 0x0d)) {
262 printk(KERN_INFO "%s: Madge MC ROM read failed (unknown card ID %02x)\n", dev->name, card->cardtype);
263 ret = -EIO;
264 goto getout3;
265 }
266
267 /* All cards except Rev 0 and 1 MC16's have 256kb of RAM */
268 if ((card->cardtype == 0x08) && (card->cardrev <= 0x01))
269 card->ramsize = 128;
270 else
271 card->ramsize = 256;
272
273 printk("%s: %s Rev %d at 0x%04lx IRQ %d\n",
274 dev->name,
275 (card->cardtype == 0x08)?MADGEMC16_CARDNAME:
276 MADGEMC32_CARDNAME, card->cardrev,
277 dev->base_addr, dev->irq);
278
279 if (card->cardtype == 0x0d)
280 printk("%s: Warning: MC32 support is experimental and highly untested\n", dev->name);
281
282 if (card->ringspeed==2) { /* Unknown */
283 printk("%s: Warning: Ring speed not set in POS -- Please run the reference disk and set it!\n", dev->name);
284 card->ringspeed = 1; /* default to 16mb */
285 }
286
287 printk("%s: RAM Size: %dKB\n", dev->name, card->ramsize);
288
289 printk("%s: Ring Speed: %dMb/sec on %s\n", dev->name,
290 (card->ringspeed)?16:4,
291 card->cabletype?"STP/DB9":"UTP/RJ-45");
292 printk("%s: Arbitration Level: %d\n", dev->name,
293 card->arblevel);
294
295 printk("%s: Burst Mode: ", dev->name);
296 switch(card->burstmode) {
297 case 0: printk("Cycle steal"); break;
298 case 1: printk("Limited burst"); break;
299 case 2: printk("Delayed release"); break;
300 case 3: printk("Immediate release"); break;
301 }
302 printk(" (%s)\n", (card->fairness)?"Unfair":"Fair");
303
304
305 /*
306 * Enable SIF before we assign the interrupt handler,
307 * just in case we get spurious interrupts that need
308 * handling.
309 */
310 outb(0, dev->base_addr + MC_CONTROL_REG0); /* sanity */
311 madgemc_setsifsel(dev, 1);
312 if (request_irq(dev->irq, madgemc_interrupt, IRQF_SHARED,
313 "madgemc", dev)) {
314 ret = -EBUSY;
315 goto getout3;
316 }
317
318 madgemc_chipset_init(dev); /* enables interrupts! */
319 madgemc_setcabletype(dev, card->cabletype);
320
321 /* Setup MCA structures */
322 mca_device_set_name(mdev, (card->cardtype == 0x08)?MADGEMC16_CARDNAME:MADGEMC32_CARDNAME);
323 mca_set_adapter_procfn(mdev->slot, madgemc_mcaproc, dev);
324
325 printk("%s: Ring Station Address: %pM\n",
326 dev->name, dev->dev_addr);
327
328 if (tmsdev_init(dev, device)) {
329 printk("%s: unable to get memory for dev->priv.\n",
330 dev->name);
331 ret = -ENOMEM;
332 goto getout4;
333 }
334 tp = netdev_priv(dev);
335
336 /*
337 * The MC16 is physically a 32bit card. However, Madge
338 * insists on calling it 16bit, so I'll assume here that
339 * they know what they're talking about. Cut off DMA
340 * at 16mb.
341 */
342 tp->setnselout = madgemc_setnselout_pins;
343 tp->sifwriteb = madgemc_sifwriteb;
344 tp->sifreadb = madgemc_sifreadb;
345 tp->sifwritew = madgemc_sifwritew;
346 tp->sifreadw = madgemc_sifreadw;
347 tp->DataRate = (card->ringspeed)?SPEED_16:SPEED_4;
348
349 memcpy(tp->ProductID, "Madge MCA 16/4 ", PROD_ID_SIZE + 1);
350
351 dev->open = madgemc_open;
352 dev->stop = madgemc_close;
353
354 tp->tmspriv = card;
355 dev_set_drvdata(device, dev);
356
357 if (register_netdev(dev) == 0)
358 return 0;
359
360 dev_set_drvdata(device, NULL);
361 ret = -ENOMEM;
362 getout4:
363 free_irq(dev->irq, dev);
364 getout3:
365 release_region(dev->base_addr-MADGEMC_SIF_OFFSET,
366 MADGEMC_IO_EXTENT);
367 getout2:
368 kfree(card);
369 getout1:
370 free_netdev(dev);
371 getout:
372 mca_device_set_claim(mdev, 0);
373 return ret;
374 }
375
376 /*
377 * Handle interrupts generated by the card
378 *
379 * The MicroChannel Madge cards need slightly more handling
380 * after an interrupt than other TMS380 cards do.
381 *
382 * First we must make sure it was this card that generated the
383 * interrupt (since interrupt sharing is allowed). Then,
384 * because we're using level-triggered interrupts (as is
385 * standard on MCA), we must toggle the interrupt line
386 * on the card in order to claim and acknowledge the interrupt.
387 * Once that is done, the interrupt should be handlable in
388 * the normal tms380tr_interrupt() routine.
389 *
390 * There's two ways we can check to see if the interrupt is ours,
391 * both with their own disadvantages...
392 *
393 * 1) Read in the SIFSTS register from the TMS controller. This
394 * is guarenteed to be accurate, however, there's a fairly
395 * large performance penalty for doing so: the Madge chips
396 * must request the register from the Eagle, the Eagle must
397 * read them from its internal bus, and then take the route
398 * back out again, for a 16bit read.
399 *
400 * 2) Use the MC_CONTROL_REG0_SINTR bit from the Madge ASICs.
401 * The major disadvantage here is that the accuracy of the
402 * bit is in question. However, it cuts out the extra read
403 * cycles it takes to read the Eagle's SIF, as its only an
404 * 8bit read, and theoretically the Madge bit is directly
405 * connected to the interrupt latch coming out of the Eagle
406 * hardware (that statement is not verified).
407 *
408 * I can't determine which of these methods has the best win. For now,
409 * we make a compromise. Use the Madge way for the first interrupt,
410 * which should be the fast-path, and then once we hit the first
411 * interrupt, keep on trying using the SIF method until we've
412 * exhausted all contiguous interrupts.
413 *
414 */
madgemc_interrupt(int irq,void * dev_id)415 static irqreturn_t madgemc_interrupt(int irq, void *dev_id)
416 {
417 int pending,reg1;
418 struct net_device *dev;
419
420 if (!dev_id) {
421 printk("madgemc_interrupt: was not passed a dev_id!\n");
422 return IRQ_NONE;
423 }
424
425 dev = (struct net_device *)dev_id;
426
427 /* Make sure its really us. -- the Madge way */
428 pending = inb(dev->base_addr + MC_CONTROL_REG0);
429 if (!(pending & MC_CONTROL_REG0_SINTR))
430 return IRQ_NONE; /* not our interrupt */
431
432 /*
433 * Since we're level-triggered, we may miss the rising edge
434 * of the next interrupt while we're off handling this one,
435 * so keep checking until the SIF verifies that it has nothing
436 * left for us to do.
437 */
438 pending = STS_SYSTEM_IRQ;
439 do {
440 if (pending & STS_SYSTEM_IRQ) {
441
442 /* Toggle the interrupt to reset the latch on card */
443 reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
444 outb(reg1 ^ MC_CONTROL_REG1_SINTEN,
445 dev->base_addr + MC_CONTROL_REG1);
446 outb(reg1, dev->base_addr + MC_CONTROL_REG1);
447
448 /* Continue handling as normal */
449 tms380tr_interrupt(irq, dev_id);
450
451 pending = SIFREADW(SIFSTS); /* restart - the SIF way */
452
453 } else
454 return IRQ_HANDLED;
455 } while (1);
456
457 return IRQ_HANDLED; /* not reachable */
458 }
459
460 /*
461 * Set the card to the prefered ring speed.
462 *
463 * Unlike newer cards, the MC16/32 have their speed selection
464 * circuit connected to the Madge ASICs and not to the TMS380
465 * NSELOUT pins. Set the ASIC bits correctly here, and return
466 * zero to leave the TMS NSELOUT bits unaffected.
467 *
468 */
madgemc_setnselout_pins(struct net_device * dev)469 static unsigned short madgemc_setnselout_pins(struct net_device *dev)
470 {
471 unsigned char reg1;
472 struct net_local *tp = netdev_priv(dev);
473
474 reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
475
476 if(tp->DataRate == SPEED_16)
477 reg1 |= MC_CONTROL_REG1_SPEED_SEL; /* add for 16mb */
478 else if (reg1 & MC_CONTROL_REG1_SPEED_SEL)
479 reg1 ^= MC_CONTROL_REG1_SPEED_SEL; /* remove for 4mb */
480 outb(reg1, dev->base_addr + MC_CONTROL_REG1);
481
482 return 0; /* no change */
483 }
484
485 /*
486 * Set the register page. This equates to the SRSX line
487 * on the TMS380Cx6.
488 *
489 * Register selection is normally done via three contiguous
490 * bits. However, some boards (such as the MC16/32) use only
491 * two bits, plus a separate bit in the glue chip. This
492 * sets the SRSX bit (the top bit). See page 4-17 in the
493 * Yellow Book for which registers are affected.
494 *
495 */
madgemc_setregpage(struct net_device * dev,int page)496 static void madgemc_setregpage(struct net_device *dev, int page)
497 {
498 static int reg1;
499
500 reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
501 if ((page == 0) && (reg1 & MC_CONTROL_REG1_SRSX)) {
502 outb(reg1 ^ MC_CONTROL_REG1_SRSX,
503 dev->base_addr + MC_CONTROL_REG1);
504 }
505 else if (page == 1) {
506 outb(reg1 | MC_CONTROL_REG1_SRSX,
507 dev->base_addr + MC_CONTROL_REG1);
508 }
509 reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
510
511 return;
512 }
513
514 /*
515 * The SIF registers are not mapped into register space by default
516 * Set this to 1 to map them, 0 to map the BIA ROM.
517 *
518 */
madgemc_setsifsel(struct net_device * dev,int val)519 static void madgemc_setsifsel(struct net_device *dev, int val)
520 {
521 unsigned int reg0;
522
523 reg0 = inb(dev->base_addr + MC_CONTROL_REG0);
524 if ((val == 0) && (reg0 & MC_CONTROL_REG0_SIFSEL)) {
525 outb(reg0 ^ MC_CONTROL_REG0_SIFSEL,
526 dev->base_addr + MC_CONTROL_REG0);
527 } else if (val == 1) {
528 outb(reg0 | MC_CONTROL_REG0_SIFSEL,
529 dev->base_addr + MC_CONTROL_REG0);
530 }
531 reg0 = inb(dev->base_addr + MC_CONTROL_REG0);
532
533 return;
534 }
535
536 /*
537 * Enable SIF interrupts
538 *
539 * This does not enable interrupts in the SIF, but rather
540 * enables SIF interrupts to be passed onto the host.
541 *
542 */
madgemc_setint(struct net_device * dev,int val)543 static void madgemc_setint(struct net_device *dev, int val)
544 {
545 unsigned int reg1;
546
547 reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
548 if ((val == 0) && (reg1 & MC_CONTROL_REG1_SINTEN)) {
549 outb(reg1 ^ MC_CONTROL_REG1_SINTEN,
550 dev->base_addr + MC_CONTROL_REG1);
551 } else if (val == 1) {
552 outb(reg1 | MC_CONTROL_REG1_SINTEN,
553 dev->base_addr + MC_CONTROL_REG1);
554 }
555
556 return;
557 }
558
559 /*
560 * Cable type is set via control register 7. Bit zero high
561 * for UTP, low for STP.
562 */
madgemc_setcabletype(struct net_device * dev,int type)563 static void madgemc_setcabletype(struct net_device *dev, int type)
564 {
565 outb((type==0)?MC_CONTROL_REG7_CABLEUTP:MC_CONTROL_REG7_CABLESTP,
566 dev->base_addr + MC_CONTROL_REG7);
567 }
568
569 /*
570 * Enable the functions of the Madge chipset needed for
571 * full working order.
572 */
madgemc_chipset_init(struct net_device * dev)573 static int madgemc_chipset_init(struct net_device *dev)
574 {
575 outb(0, dev->base_addr + MC_CONTROL_REG1); /* pull SRESET low */
576 tms380tr_wait(100); /* wait for card to reset */
577
578 /* bring back into normal operating mode */
579 outb(MC_CONTROL_REG1_NSRESET, dev->base_addr + MC_CONTROL_REG1);
580
581 /* map SIF registers */
582 madgemc_setsifsel(dev, 1);
583
584 /* enable SIF interrupts */
585 madgemc_setint(dev, 1);
586
587 return 0;
588 }
589
590 /*
591 * Disable the board, and put back into power-up state.
592 */
madgemc_chipset_close(struct net_device * dev)593 static void madgemc_chipset_close(struct net_device *dev)
594 {
595 /* disable interrupts */
596 madgemc_setint(dev, 0);
597 /* unmap SIF registers */
598 madgemc_setsifsel(dev, 0);
599
600 return;
601 }
602
603 /*
604 * Read the card type (MC16 or MC32) from the card.
605 *
606 * The configuration registers are stored in two separate
607 * pages. Pages are flipped by clearing bit 3 of CONTROL_REG0 (PAGE)
608 * for page zero, or setting bit 3 for page one.
609 *
610 * Page zero contains the following data:
611 * Byte 0: Manufacturer ID (0x4D -- ASCII "M")
612 * Byte 1: Card type:
613 * 0x08 for MC16
614 * 0x0D for MC32
615 * Byte 2: Card revision
616 * Byte 3: Mirror of POS config register 0
617 * Byte 4: Mirror of POS 1
618 * Byte 5: Mirror of POS 2
619 *
620 * Page one contains the following data:
621 * Byte 0: Unused
622 * Byte 1-6: BIA, MSB to LSB.
623 *
624 * Note that to read the BIA, we must unmap the SIF registers
625 * by clearing bit 2 of CONTROL_REG0 (SIFSEL), as the data
626 * will reside in the same logical location. For this reason,
627 * _never_ read the BIA while the Eagle processor is running!
628 * The SIF will be completely inaccessible until the BIA operation
629 * is complete.
630 *
631 */
madgemc_read_rom(struct net_device * dev,struct card_info * card)632 static void madgemc_read_rom(struct net_device *dev, struct card_info *card)
633 {
634 unsigned long ioaddr;
635 unsigned char reg0, reg1, tmpreg0, i;
636
637 ioaddr = dev->base_addr;
638
639 reg0 = inb(ioaddr + MC_CONTROL_REG0);
640 reg1 = inb(ioaddr + MC_CONTROL_REG1);
641
642 /* Switch to page zero and unmap SIF */
643 tmpreg0 = reg0 & ~(MC_CONTROL_REG0_PAGE + MC_CONTROL_REG0_SIFSEL);
644 outb(tmpreg0, ioaddr + MC_CONTROL_REG0);
645
646 card->manid = inb(ioaddr + MC_ROM_MANUFACTURERID);
647 card->cardtype = inb(ioaddr + MC_ROM_ADAPTERID);
648 card->cardrev = inb(ioaddr + MC_ROM_REVISION);
649
650 /* Switch to rom page one */
651 outb(tmpreg0 | MC_CONTROL_REG0_PAGE, ioaddr + MC_CONTROL_REG0);
652
653 /* Read BIA */
654 dev->addr_len = 6;
655 for (i = 0; i < 6; i++)
656 dev->dev_addr[i] = inb(ioaddr + MC_ROM_BIA_START + i);
657
658 /* Restore original register values */
659 outb(reg0, ioaddr + MC_CONTROL_REG0);
660 outb(reg1, ioaddr + MC_CONTROL_REG1);
661
662 return;
663 }
664
madgemc_open(struct net_device * dev)665 static int madgemc_open(struct net_device *dev)
666 {
667 /*
668 * Go ahead and reinitialize the chipset again, just to
669 * make sure we didn't get left in a bad state.
670 */
671 madgemc_chipset_init(dev);
672 tms380tr_open(dev);
673 return 0;
674 }
675
madgemc_close(struct net_device * dev)676 static int madgemc_close(struct net_device *dev)
677 {
678 tms380tr_close(dev);
679 madgemc_chipset_close(dev);
680 return 0;
681 }
682
683 /*
684 * Give some details available from /proc/mca/slotX
685 */
madgemc_mcaproc(char * buf,int slot,void * d)686 static int madgemc_mcaproc(char *buf, int slot, void *d)
687 {
688 struct net_device *dev = (struct net_device *)d;
689 struct net_local *tp = netdev_priv(dev);
690 struct card_info *curcard = tp->tmspriv;
691 int len = 0;
692
693 len += sprintf(buf+len, "-------\n");
694 if (curcard) {
695 struct net_local *tp = netdev_priv(dev);
696
697 len += sprintf(buf+len, "Card Revision: %d\n", curcard->cardrev);
698 len += sprintf(buf+len, "RAM Size: %dkb\n", curcard->ramsize);
699 len += sprintf(buf+len, "Cable type: %s\n", (curcard->cabletype)?"STP/DB9":"UTP/RJ-45");
700 len += sprintf(buf+len, "Configured ring speed: %dMb/sec\n", (curcard->ringspeed)?16:4);
701 len += sprintf(buf+len, "Running ring speed: %dMb/sec\n", (tp->DataRate==SPEED_16)?16:4);
702 len += sprintf(buf+len, "Device: %s\n", dev->name);
703 len += sprintf(buf+len, "IO Port: 0x%04lx\n", dev->base_addr);
704 len += sprintf(buf+len, "IRQ: %d\n", dev->irq);
705 len += sprintf(buf+len, "Arbitration Level: %d\n", curcard->arblevel);
706 len += sprintf(buf+len, "Burst Mode: ");
707 switch(curcard->burstmode) {
708 case 0: len += sprintf(buf+len, "Cycle steal"); break;
709 case 1: len += sprintf(buf+len, "Limited burst"); break;
710 case 2: len += sprintf(buf+len, "Delayed release"); break;
711 case 3: len += sprintf(buf+len, "Immediate release"); break;
712 }
713 len += sprintf(buf+len, " (%s)\n", (curcard->fairness)?"Unfair":"Fair");
714
715 len += sprintf(buf+len, "Ring Station Address: %pM\n",
716 dev->dev_addr);
717 } else
718 len += sprintf(buf+len, "Card not configured\n");
719
720 return len;
721 }
722
madgemc_remove(struct device * device)723 static int __devexit madgemc_remove(struct device *device)
724 {
725 struct net_device *dev = dev_get_drvdata(device);
726 struct net_local *tp;
727 struct card_info *card;
728
729 BUG_ON(!dev);
730
731 tp = netdev_priv(dev);
732 card = tp->tmspriv;
733 kfree(card);
734 tp->tmspriv = NULL;
735
736 unregister_netdev(dev);
737 release_region(dev->base_addr-MADGEMC_SIF_OFFSET, MADGEMC_IO_EXTENT);
738 free_irq(dev->irq, dev);
739 tmsdev_term(dev);
740 free_netdev(dev);
741 dev_set_drvdata(device, NULL);
742
743 return 0;
744 }
745
746 static short madgemc_adapter_ids[] __initdata = {
747 0x002d,
748 0x0000
749 };
750
751 static struct mca_driver madgemc_driver = {
752 .id_table = madgemc_adapter_ids,
753 .driver = {
754 .name = "madgemc",
755 .bus = &mca_bus_type,
756 .probe = madgemc_probe,
757 .remove = __devexit_p(madgemc_remove),
758 },
759 };
760
madgemc_init(void)761 static int __init madgemc_init (void)
762 {
763 return mca_register_driver (&madgemc_driver);
764 }
765
madgemc_exit(void)766 static void __exit madgemc_exit (void)
767 {
768 mca_unregister_driver (&madgemc_driver);
769 }
770
771 module_init(madgemc_init);
772 module_exit(madgemc_exit);
773
774 MODULE_LICENSE("GPL");
775
776