1 /*
2 *
3 * Programmable Interrupt Controller functions for the Freescale MPC52xx.
4 *
5 * Copyright (C) 2008 Secret Lab Technologies Ltd.
6 * Copyright (C) 2006 bplan GmbH
7 * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
8 * Copyright (C) 2003 Montavista Software, Inc
9 *
10 * Based on the code from the 2.4 kernel by
11 * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 *
17 */
18
19 /*
20 * This is the device driver for the MPC5200 interrupt controller.
21 *
22 * hardware overview
23 * -----------------
24 * The MPC5200 interrupt controller groups the all interrupt sources into
25 * three groups called 'critical', 'main', and 'peripheral'. The critical
26 * group has 3 irqs, External IRQ0, slice timer 0 irq, and wake from deep
27 * sleep. Main group include the other 3 external IRQs, slice timer 1, RTC,
28 * gpios, and the general purpose timers. Peripheral group contains the
29 * remaining irq sources from all of the on-chip peripherals (PSCs, Ethernet,
30 * USB, DMA, etc).
31 *
32 * virqs
33 * -----
34 * The Linux IRQ subsystem requires that each irq source be assigned a
35 * system wide unique IRQ number starting at 1 (0 means no irq). Since
36 * systems can have multiple interrupt controllers, the virtual IRQ (virq)
37 * infrastructure lets each interrupt controller to define a local set
38 * of IRQ numbers and the virq infrastructure maps those numbers into
39 * a unique range of the global IRQ# space.
40 *
41 * To define a range of virq numbers for this controller, this driver first
42 * assigns a number to each of the irq groups (called the level 1 or L1
43 * value). Within each group individual irq sources are also assigned a
44 * number, as defined by the MPC5200 user guide, and refers to it as the
45 * level 2 or L2 value. The virq number is determined by shifting up the
46 * L1 value by MPC52xx_IRQ_L1_OFFSET and ORing it with the L2 value.
47 *
48 * For example, the TMR0 interrupt is irq 9 in the main group. The
49 * virq for TMR0 is calculated by ((1 << MPC52xx_IRQ_L1_OFFSET) | 9).
50 *
51 * The observant reader will also notice that this driver defines a 4th
52 * interrupt group called 'bestcomm'. The bestcomm group isn't physically
53 * part of the MPC5200 interrupt controller, but it is used here to assign
54 * a separate virq number for each bestcomm task (since any of the 16
55 * bestcomm tasks can cause the bestcomm interrupt to be raised). When a
56 * bestcomm interrupt occurs (peripheral group, irq 0) this driver determines
57 * which task needs servicing and returns the irq number for that task. This
58 * allows drivers which use bestcomm to define their own interrupt handlers.
59 *
60 * irq_chip structures
61 * -------------------
62 * For actually manipulating IRQs (masking, enabling, clearing, etc) this
63 * driver defines four separate 'irq_chip' structures, one for the main
64 * group, one for the peripherals group, one for the bestcomm group and one
65 * for external interrupts. The irq_chip structures provide the hooks needed
66 * to manipulate each IRQ source, and since each group is has a separate set
67 * of registers for controlling the irq, it makes sense to divide up the
68 * hooks along those lines.
69 *
70 * You'll notice that there is not an irq_chip for the critical group and
71 * you'll also notice that there is an irq_chip defined for external
72 * interrupts even though there is no external interrupt group. The reason
73 * for this is that the four external interrupts are all managed with the same
74 * register even though one of the external IRQs is in the critical group and
75 * the other three are in the main group. For this reason it makes sense for
76 * the 4 external irqs to be managed using a separate set of hooks. The
77 * reason there is no crit irq_chip is that of the 3 irqs in the critical
78 * group, only external interrupt is actually support at this time by this
79 * driver and since external interrupt is the only one used, it can just
80 * be directed to make use of the external irq irq_chip.
81 *
82 * device tree bindings
83 * --------------------
84 * The device tree bindings for this controller reflect the two level
85 * organization of irqs in the device. #interrupt-cells = <3> where the
86 * first cell is the group number [0..3], the second cell is the irq
87 * number in the group, and the third cell is the sense type (level/edge).
88 * For reference, the following is a list of the interrupt property values
89 * associated with external interrupt sources on the MPC5200 (just because
90 * it is non-obvious to determine what the interrupts property should be
91 * when reading the mpc5200 manual and it is a frequently asked question).
92 *
93 * External interrupts:
94 * <0 0 n> external irq0, n is sense (n=0: level high,
95 * <1 1 n> external irq1, n is sense n=1: edge rising,
96 * <1 2 n> external irq2, n is sense n=2: edge falling,
97 * <1 3 n> external irq3, n is sense n=3: level low)
98 */
99 #undef DEBUG
100
101 #include <linux/interrupt.h>
102 #include <linux/irq.h>
103 #include <linux/of.h>
104 #include <asm/io.h>
105 #include <asm/prom.h>
106 #include <asm/mpc52xx.h>
107
108 /* HW IRQ mapping */
109 #define MPC52xx_IRQ_L1_CRIT (0)
110 #define MPC52xx_IRQ_L1_MAIN (1)
111 #define MPC52xx_IRQ_L1_PERP (2)
112 #define MPC52xx_IRQ_L1_SDMA (3)
113
114 #define MPC52xx_IRQ_L1_OFFSET (6)
115 #define MPC52xx_IRQ_L1_MASK (0x00c0)
116 #define MPC52xx_IRQ_L2_MASK (0x003f)
117
118 #define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0)
119
120
121 /* MPC5200 device tree match tables */
122 static struct of_device_id mpc52xx_pic_ids[] __initdata = {
123 { .compatible = "fsl,mpc5200-pic", },
124 { .compatible = "mpc5200-pic", },
125 {}
126 };
127 static struct of_device_id mpc52xx_sdma_ids[] __initdata = {
128 { .compatible = "fsl,mpc5200-bestcomm", },
129 { .compatible = "mpc5200-bestcomm", },
130 {}
131 };
132
133 static struct mpc52xx_intr __iomem *intr;
134 static struct mpc52xx_sdma __iomem *sdma;
135 static struct irq_host *mpc52xx_irqhost = NULL;
136
137 static unsigned char mpc52xx_map_senses[4] = {
138 IRQ_TYPE_LEVEL_HIGH,
139 IRQ_TYPE_EDGE_RISING,
140 IRQ_TYPE_EDGE_FALLING,
141 IRQ_TYPE_LEVEL_LOW,
142 };
143
144 /* Utility functions */
io_be_setbit(u32 __iomem * addr,int bitno)145 static inline void io_be_setbit(u32 __iomem *addr, int bitno)
146 {
147 out_be32(addr, in_be32(addr) | (1 << bitno));
148 }
149
io_be_clrbit(u32 __iomem * addr,int bitno)150 static inline void io_be_clrbit(u32 __iomem *addr, int bitno)
151 {
152 out_be32(addr, in_be32(addr) & ~(1 << bitno));
153 }
154
155 /*
156 * IRQ[0-3] interrupt irq_chip
157 */
mpc52xx_extirq_mask(unsigned int virq)158 static void mpc52xx_extirq_mask(unsigned int virq)
159 {
160 int irq;
161 int l2irq;
162
163 irq = irq_map[virq].hwirq;
164 l2irq = irq & MPC52xx_IRQ_L2_MASK;
165
166 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
167
168 io_be_clrbit(&intr->ctrl, 11 - l2irq);
169 }
170
mpc52xx_extirq_unmask(unsigned int virq)171 static void mpc52xx_extirq_unmask(unsigned int virq)
172 {
173 int irq;
174 int l2irq;
175
176 irq = irq_map[virq].hwirq;
177 l2irq = irq & MPC52xx_IRQ_L2_MASK;
178
179 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
180
181 io_be_setbit(&intr->ctrl, 11 - l2irq);
182 }
183
mpc52xx_extirq_ack(unsigned int virq)184 static void mpc52xx_extirq_ack(unsigned int virq)
185 {
186 int irq;
187 int l2irq;
188
189 irq = irq_map[virq].hwirq;
190 l2irq = irq & MPC52xx_IRQ_L2_MASK;
191
192 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
193
194 io_be_setbit(&intr->ctrl, 27-l2irq);
195 }
196
mpc52xx_extirq_set_type(unsigned int virq,unsigned int flow_type)197 static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type)
198 {
199 struct irq_desc *desc = get_irq_desc(virq);
200 u32 ctrl_reg, type;
201 int irq;
202 int l2irq;
203
204 irq = irq_map[virq].hwirq;
205 l2irq = irq & MPC52xx_IRQ_L2_MASK;
206
207 pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__, irq, l2irq, flow_type);
208
209 switch (flow_type) {
210 case IRQF_TRIGGER_HIGH:
211 type = 0;
212 break;
213 case IRQF_TRIGGER_RISING:
214 type = 1;
215 break;
216 case IRQF_TRIGGER_FALLING:
217 type = 2;
218 break;
219 case IRQF_TRIGGER_LOW:
220 type = 3;
221 break;
222 default:
223 type = 0;
224 }
225
226 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
227 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
228 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
229 desc->status |= IRQ_LEVEL;
230
231 ctrl_reg = in_be32(&intr->ctrl);
232 ctrl_reg &= ~(0x3 << (22 - (l2irq * 2)));
233 ctrl_reg |= (type << (22 - (l2irq * 2)));
234 out_be32(&intr->ctrl, ctrl_reg);
235
236 return 0;
237 }
238
239 static struct irq_chip mpc52xx_extirq_irqchip = {
240 .typename = "MPC52xx External",
241 .mask = mpc52xx_extirq_mask,
242 .unmask = mpc52xx_extirq_unmask,
243 .ack = mpc52xx_extirq_ack,
244 .set_type = mpc52xx_extirq_set_type,
245 };
246
247 /*
248 * Main interrupt irq_chip
249 */
mpc52xx_main_mask(unsigned int virq)250 static void mpc52xx_main_mask(unsigned int virq)
251 {
252 int irq;
253 int l2irq;
254
255 irq = irq_map[virq].hwirq;
256 l2irq = irq & MPC52xx_IRQ_L2_MASK;
257
258 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
259
260 io_be_setbit(&intr->main_mask, 16 - l2irq);
261 }
262
mpc52xx_main_unmask(unsigned int virq)263 static void mpc52xx_main_unmask(unsigned int virq)
264 {
265 int irq;
266 int l2irq;
267
268 irq = irq_map[virq].hwirq;
269 l2irq = irq & MPC52xx_IRQ_L2_MASK;
270
271 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
272
273 io_be_clrbit(&intr->main_mask, 16 - l2irq);
274 }
275
276 static struct irq_chip mpc52xx_main_irqchip = {
277 .typename = "MPC52xx Main",
278 .mask = mpc52xx_main_mask,
279 .mask_ack = mpc52xx_main_mask,
280 .unmask = mpc52xx_main_unmask,
281 };
282
283 /*
284 * Peripherals interrupt irq_chip
285 */
mpc52xx_periph_mask(unsigned int virq)286 static void mpc52xx_periph_mask(unsigned int virq)
287 {
288 int irq;
289 int l2irq;
290
291 irq = irq_map[virq].hwirq;
292 l2irq = irq & MPC52xx_IRQ_L2_MASK;
293
294 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
295
296 io_be_setbit(&intr->per_mask, 31 - l2irq);
297 }
298
mpc52xx_periph_unmask(unsigned int virq)299 static void mpc52xx_periph_unmask(unsigned int virq)
300 {
301 int irq;
302 int l2irq;
303
304 irq = irq_map[virq].hwirq;
305 l2irq = irq & MPC52xx_IRQ_L2_MASK;
306
307 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
308
309 io_be_clrbit(&intr->per_mask, 31 - l2irq);
310 }
311
312 static struct irq_chip mpc52xx_periph_irqchip = {
313 .typename = "MPC52xx Peripherals",
314 .mask = mpc52xx_periph_mask,
315 .mask_ack = mpc52xx_periph_mask,
316 .unmask = mpc52xx_periph_unmask,
317 };
318
319 /*
320 * SDMA interrupt irq_chip
321 */
mpc52xx_sdma_mask(unsigned int virq)322 static void mpc52xx_sdma_mask(unsigned int virq)
323 {
324 int irq;
325 int l2irq;
326
327 irq = irq_map[virq].hwirq;
328 l2irq = irq & MPC52xx_IRQ_L2_MASK;
329
330 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
331
332 io_be_setbit(&sdma->IntMask, l2irq);
333 }
334
mpc52xx_sdma_unmask(unsigned int virq)335 static void mpc52xx_sdma_unmask(unsigned int virq)
336 {
337 int irq;
338 int l2irq;
339
340 irq = irq_map[virq].hwirq;
341 l2irq = irq & MPC52xx_IRQ_L2_MASK;
342
343 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
344
345 io_be_clrbit(&sdma->IntMask, l2irq);
346 }
347
mpc52xx_sdma_ack(unsigned int virq)348 static void mpc52xx_sdma_ack(unsigned int virq)
349 {
350 int irq;
351 int l2irq;
352
353 irq = irq_map[virq].hwirq;
354 l2irq = irq & MPC52xx_IRQ_L2_MASK;
355
356 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
357
358 out_be32(&sdma->IntPend, 1 << l2irq);
359 }
360
361 static struct irq_chip mpc52xx_sdma_irqchip = {
362 .typename = "MPC52xx SDMA",
363 .mask = mpc52xx_sdma_mask,
364 .unmask = mpc52xx_sdma_unmask,
365 .ack = mpc52xx_sdma_ack,
366 };
367
368 /**
369 * mpc52xx_irqhost_xlate - translate virq# from device tree interrupts property
370 */
mpc52xx_irqhost_xlate(struct irq_host * h,struct device_node * ct,u32 * intspec,unsigned int intsize,irq_hw_number_t * out_hwirq,unsigned int * out_flags)371 static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
372 u32 *intspec, unsigned int intsize,
373 irq_hw_number_t *out_hwirq,
374 unsigned int *out_flags)
375 {
376 int intrvect_l1;
377 int intrvect_l2;
378 int intrvect_type;
379 int intrvect_linux;
380
381 if (intsize != 3)
382 return -1;
383
384 intrvect_l1 = (int)intspec[0];
385 intrvect_l2 = (int)intspec[1];
386 intrvect_type = (int)intspec[2];
387
388 intrvect_linux = (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) &
389 MPC52xx_IRQ_L1_MASK;
390 intrvect_linux |= intrvect_l2 & MPC52xx_IRQ_L2_MASK;
391
392 pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1,
393 intrvect_l2);
394
395 *out_hwirq = intrvect_linux;
396 *out_flags = mpc52xx_map_senses[intrvect_type];
397
398 return 0;
399 }
400
401 /**
402 * mpc52xx_irqx_gettype - determine the IRQ sense type (level/edge)
403 *
404 * Only external IRQs need this.
405 */
mpc52xx_irqx_gettype(int irq)406 static int mpc52xx_irqx_gettype(int irq)
407 {
408 int type;
409 u32 ctrl_reg;
410
411 ctrl_reg = in_be32(&intr->ctrl);
412 type = (ctrl_reg >> (22 - irq * 2)) & 0x3;
413
414 return mpc52xx_map_senses[type];
415 }
416
417 /**
418 * mpc52xx_irqhost_map - Hook to map from virq to an irq_chip structure
419 */
mpc52xx_irqhost_map(struct irq_host * h,unsigned int virq,irq_hw_number_t irq)420 static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
421 irq_hw_number_t irq)
422 {
423 int l1irq;
424 int l2irq;
425 struct irq_chip *good_irqchip;
426 void *good_handle;
427 int type;
428
429 l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
430 l2irq = irq & MPC52xx_IRQ_L2_MASK;
431
432 /*
433 * Most of ours IRQs will be level low
434 * Only external IRQs on some platform may be others
435 */
436 type = IRQ_TYPE_LEVEL_LOW;
437
438 switch (l1irq) {
439 case MPC52xx_IRQ_L1_CRIT:
440 pr_debug("%s: Critical. l2=%x\n", __func__, l2irq);
441
442 BUG_ON(l2irq != 0);
443
444 type = mpc52xx_irqx_gettype(l2irq);
445 good_irqchip = &mpc52xx_extirq_irqchip;
446 break;
447
448 case MPC52xx_IRQ_L1_MAIN:
449 pr_debug("%s: Main IRQ[1-3] l2=%x\n", __func__, l2irq);
450
451 if ((l2irq >= 1) && (l2irq <= 3)) {
452 type = mpc52xx_irqx_gettype(l2irq);
453 good_irqchip = &mpc52xx_extirq_irqchip;
454 } else {
455 good_irqchip = &mpc52xx_main_irqchip;
456 }
457 break;
458
459 case MPC52xx_IRQ_L1_PERP:
460 pr_debug("%s: Peripherals. l2=%x\n", __func__, l2irq);
461 good_irqchip = &mpc52xx_periph_irqchip;
462 break;
463
464 case MPC52xx_IRQ_L1_SDMA:
465 pr_debug("%s: SDMA. l2=%x\n", __func__, l2irq);
466 good_irqchip = &mpc52xx_sdma_irqchip;
467 break;
468
469 default:
470 pr_err("%s: invalid virq requested (0x%x)\n", __func__, virq);
471 return -EINVAL;
472 }
473
474 switch (type) {
475 case IRQ_TYPE_EDGE_FALLING:
476 case IRQ_TYPE_EDGE_RISING:
477 good_handle = handle_edge_irq;
478 break;
479 default:
480 good_handle = handle_level_irq;
481 }
482
483 set_irq_chip_and_handler(virq, good_irqchip, good_handle);
484
485 pr_debug("%s: virq=%x, hw=%x. type=%x\n", __func__, virq,
486 (int)irq, type);
487
488 return 0;
489 }
490
491 static struct irq_host_ops mpc52xx_irqhost_ops = {
492 .xlate = mpc52xx_irqhost_xlate,
493 .map = mpc52xx_irqhost_map,
494 };
495
496 /**
497 * mpc52xx_init_irq - Initialize and register with the virq subsystem
498 *
499 * Hook for setting up IRQs on an mpc5200 system. A pointer to this function
500 * is to be put into the machine definition structure.
501 *
502 * This function searches the device tree for an MPC5200 interrupt controller,
503 * initializes it, and registers it with the virq subsystem.
504 */
mpc52xx_init_irq(void)505 void __init mpc52xx_init_irq(void)
506 {
507 u32 intr_ctrl;
508 struct device_node *picnode;
509 struct device_node *np;
510
511 /* Remap the necessary zones */
512 picnode = of_find_matching_node(NULL, mpc52xx_pic_ids);
513 intr = of_iomap(picnode, 0);
514 if (!intr)
515 panic(__FILE__ ": find_and_map failed on 'mpc5200-pic'. "
516 "Check node !");
517
518 np = of_find_matching_node(NULL, mpc52xx_sdma_ids);
519 sdma = of_iomap(np, 0);
520 of_node_put(np);
521 if (!sdma)
522 panic(__FILE__ ": find_and_map failed on 'mpc5200-bestcomm'. "
523 "Check node !");
524
525 /* Disable all interrupt sources. */
526 out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
527 out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
528 out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
529 out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
530 intr_ctrl = in_be32(&intr->ctrl);
531 intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
532 intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
533 0x00001000 | /* MEE master external enable */
534 0x00000000 | /* 0 means disable IRQ 0-3 */
535 0x00000001; /* CEb route critical normally */
536 out_be32(&intr->ctrl, intr_ctrl);
537
538 /* Zero a bunch of the priority settings. */
539 out_be32(&intr->per_pri1, 0);
540 out_be32(&intr->per_pri2, 0);
541 out_be32(&intr->per_pri3, 0);
542 out_be32(&intr->main_pri1, 0);
543 out_be32(&intr->main_pri2, 0);
544
545 /*
546 * As last step, add an irq host to translate the real
547 * hw irq information provided by the ofw to linux virq
548 */
549 mpc52xx_irqhost = irq_alloc_host(picnode, IRQ_HOST_MAP_LINEAR,
550 MPC52xx_IRQ_HIGHTESTHWIRQ,
551 &mpc52xx_irqhost_ops, -1);
552
553 if (!mpc52xx_irqhost)
554 panic(__FILE__ ": Cannot allocate the IRQ host\n");
555
556 irq_set_default_host(mpc52xx_irqhost);
557
558 pr_info("MPC52xx PIC is up and running!\n");
559 }
560
561 /**
562 * mpc52xx_get_irq - Get pending interrupt number hook function
563 *
564 * Called by the interupt handler to determine what IRQ handler needs to be
565 * executed.
566 *
567 * Status of pending interrupts is determined by reading the encoded status
568 * register. The encoded status register has three fields; one for each of the
569 * types of interrupts defined by the controller - 'critical', 'main' and
570 * 'peripheral'. This function reads the status register and returns the IRQ
571 * number associated with the highest priority pending interrupt. 'Critical'
572 * interrupts have the highest priority, followed by 'main' interrupts, and
573 * then 'peripheral'.
574 *
575 * The mpc5200 interrupt controller can be configured to boost the priority
576 * of individual 'peripheral' interrupts. If this is the case then a special
577 * value will appear in either the crit or main fields indicating a high
578 * or medium priority peripheral irq has occurred.
579 *
580 * This function checks each of the 3 irq request fields and returns the
581 * first pending interrupt that it finds.
582 *
583 * This function also identifies a 4th type of interrupt; 'bestcomm'. Each
584 * bestcomm DMA task can raise the bestcomm peripheral interrupt. When this
585 * occurs at task-specific IRQ# is decoded so that each task can have its
586 * own IRQ handler.
587 */
mpc52xx_get_irq(void)588 unsigned int mpc52xx_get_irq(void)
589 {
590 u32 status;
591 int irq = NO_IRQ_IGNORE;
592
593 status = in_be32(&intr->enc_status);
594 if (status & 0x00000400) { /* critical */
595 irq = (status >> 8) & 0x3;
596 if (irq == 2) /* high priority peripheral */
597 goto peripheral;
598 irq |= (MPC52xx_IRQ_L1_CRIT << MPC52xx_IRQ_L1_OFFSET);
599 } else if (status & 0x00200000) { /* main */
600 irq = (status >> 16) & 0x1f;
601 if (irq == 4) /* low priority peripheral */
602 goto peripheral;
603 irq |= (MPC52xx_IRQ_L1_MAIN << MPC52xx_IRQ_L1_OFFSET);
604 } else if (status & 0x20000000) { /* peripheral */
605 peripheral:
606 irq = (status >> 24) & 0x1f;
607 if (irq == 0) { /* bestcomm */
608 status = in_be32(&sdma->IntPend);
609 irq = ffs(status) - 1;
610 irq |= (MPC52xx_IRQ_L1_SDMA << MPC52xx_IRQ_L1_OFFSET);
611 } else {
612 irq |= (MPC52xx_IRQ_L1_PERP << MPC52xx_IRQ_L1_OFFSET);
613 }
614 }
615
616 pr_debug("%s: irq=%x. virq=%d\n", __func__, irq,
617 irq_linear_revmap(mpc52xx_irqhost, irq));
618
619 return irq_linear_revmap(mpc52xx_irqhost, irq);
620 }
621