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Searched refs:ANOMALY_05000158_WORKAROUND (Results 1 – 3 of 3) sorted by relevance

/arch/blackfin/include/asm/
Dcplb.h43 #define ANOMALY_05000158_WORKAROUND 0x200 macro
45 #define ANOMALY_05000158_WORKAROUND 0x0 macro
48 …CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
77 #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
/arch/blackfin/kernel/cplb-mpu/
Dcplbinit.c50 i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; in generate_cplb_tables_cpu()
Dcplbmgr.c155 d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; in dcplb_miss()
245 i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; in icplb_miss()