1 /* 2 * File: include/asm-blackfin/mach-bf527/anomaly.h 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 4 * 5 * Copyright (C) 2004-2009 Analog Devices Inc. 6 * Licensed under the GPL-2 or later. 7 */ 8 9 /* This file shoule be up to date with: 10 * - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List 11 * - Revision E, 08/18/2008; ADSP-BF527 Blackfin Processor Anomaly List 12 */ 13 14 #ifndef _MACH_ANOMALY_H_ 15 #define _MACH_ANOMALY_H_ 16 17 #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) 18 # define ANOMALY_BF526 1 19 #else 20 # define ANOMALY_BF526 0 21 #endif 22 #if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__) 23 # define ANOMALY_BF527 1 24 #else 25 # define ANOMALY_BF527 0 26 #endif 27 28 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ 29 #define ANOMALY_05000074 (1) 30 /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ 31 #define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ 32 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 33 #define ANOMALY_05000122 (1) 34 /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ 35 #define ANOMALY_05000245 (1) 36 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 37 #define ANOMALY_05000265 (1) 38 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 39 #define ANOMALY_05000310 (1) 40 /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ 41 #define ANOMALY_05000313 (__SILICON_REVISION__ < 2) 42 /* Incorrect Access of OTP_STATUS During otp_write() Function */ 43 #define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 44 /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ 45 #define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 46 /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ 47 #define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 48 /* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ 49 #define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 50 /* USB Calibration Value Is Not Initialized */ 51 #define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 52 /* USB Calibration Value to use */ 53 #define ANOMALY_05000346_value 0xE510 54 /* Preboot Routine Incorrectly Alters Reset Value of USB Register */ 55 #define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 56 /* Security Features Are Not Functional */ 57 #define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1) 58 /* bfrom_SysControl() Firmware Function Performs Improper System Reset */ 59 #define ANOMALY_05000353 (ANOMALY_BF526) 60 /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ 61 #define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 62 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ 63 #define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 64 /* Incorrect Revision Number in DSPID Register */ 65 #define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1) 66 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ 67 #define ANOMALY_05000366 (1) 68 /* Incorrect Default CSEL Value in PLL_DIV */ 69 #define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 70 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ 71 #define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 72 /* Authentication Fails To Initiate */ 73 #define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 74 /* Data Read From L3 Memory by USB DMA May be Corrupted */ 75 #define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 76 /* 8-Bit NAND Flash Boot Mode Not Functional */ 77 #define ANOMALY_05000382 (__SILICON_REVISION__ < 2) 78 /* Host Must Not Read Back During Host DMA Boot */ 79 #define ANOMALY_05000384 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 80 /* Boot from OTP Memory Not Functional */ 81 #define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 82 /* bfrom_SysControl() Firmware Routine Not Functional */ 83 #define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 84 /* Programmable Preboot Settings Not Functional */ 85 #define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 86 /* CRC32 Checksum Support Not Functional */ 87 #define ANOMALY_05000388 (__SILICON_REVISION__ < 2) 88 /* Reset Vector Must Not Be in SDRAM Memory Space */ 89 #define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 90 /* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ 91 #define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 92 /* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ 93 #define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 94 /* Log Buffer Not Functional */ 95 #define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 96 /* Hook Routine Not Functional */ 97 #define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 98 /* Header Indirect Bit Not Functional */ 99 #define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 100 /* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ 101 #define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 102 /* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */ 103 #define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 104 /* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */ 105 #define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 106 /* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ 107 #define ANOMALY_05000401 (__SILICON_REVISION__ < 2) 108 /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ 109 #define ANOMALY_05000403 (__SILICON_REVISION__ < 2) 110 /* Lockbox SESR Disallows Certain User Interrupts */ 111 #define ANOMALY_05000404 (__SILICON_REVISION__ < 2) 112 /* Lockbox SESR Firmware Does Not Save/Restore Full Context */ 113 #define ANOMALY_05000405 (1) 114 /* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ 115 #define ANOMALY_05000407 (__SILICON_REVISION__ < 2) 116 /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ 117 #define ANOMALY_05000408 (1) 118 /* Lockbox firmware leaves MDMA0 channel enabled */ 119 #define ANOMALY_05000409 (__SILICON_REVISION__ < 2) 120 /* Incorrect Default Internal Voltage Regulator Setting */ 121 #define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 122 /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ 123 #define ANOMALY_05000411 (__SILICON_REVISION__ < 2) 124 /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ 125 #define ANOMALY_05000414 (__SILICON_REVISION__ < 2) 126 /* DEB2_URGENT Bit Not Functional */ 127 #define ANOMALY_05000415 (__SILICON_REVISION__ < 2) 128 /* Speculative Fetches Can Cause Undesired External FIFO Operations */ 129 #define ANOMALY_05000416 (1) 130 /* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */ 131 #define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 132 /* tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */ 133 #define ANOMALY_05000418 (__SILICON_REVISION__ < 2) 134 /* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */ 135 #define ANOMALY_05000420 (__SILICON_REVISION__ < 2) 136 /* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */ 137 #define ANOMALY_05000421 (1) 138 /* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */ 139 #define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) 140 /* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */ 141 #define ANOMALY_05000423 (__SILICON_REVISION__ < 2) 142 /* Internal Voltage Regulator Not Trimmed */ 143 #define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) 144 /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ 145 #define ANOMALY_05000425 (__SILICON_REVISION__ < 2) 146 /* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */ 147 #define ANOMALY_05000426 (1) 148 /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */ 149 #define ANOMALY_05000429 (__SILICON_REVISION__ < 2) 150 /* Software System Reset Corrupts PLL_LOCKCNT Register */ 151 #define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) 152 /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ 153 #define ANOMALY_05000432 (ANOMALY_BF526) 154 /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ 155 #define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527) 156 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 157 #define ANOMALY_05000443 (1) 158 159 /* Anomalies that don't exist on this proc */ 160 #define ANOMALY_05000125 (0) 161 #define ANOMALY_05000158 (0) 162 #define ANOMALY_05000183 (0) 163 #define ANOMALY_05000198 (0) 164 #define ANOMALY_05000230 (0) 165 #define ANOMALY_05000244 (0) 166 #define ANOMALY_05000261 (0) 167 #define ANOMALY_05000263 (0) 168 #define ANOMALY_05000266 (0) 169 #define ANOMALY_05000273 (0) 170 #define ANOMALY_05000278 (0) 171 #define ANOMALY_05000285 (0) 172 #define ANOMALY_05000305 (0) 173 #define ANOMALY_05000307 (0) 174 #define ANOMALY_05000311 (0) 175 #define ANOMALY_05000312 (0) 176 #define ANOMALY_05000323 (0) 177 #define ANOMALY_05000363 (0) 178 #define ANOMALY_05000412 (0) 179 #define ANOMALY_05000447 (0) 180 #define ANOMALY_05000448 (0) 181 182 #endif 183