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Searched refs:ARM_CKCTL (Results 1 – 5 of 5) sorted by relevance

/arch/arm/mach-omap1/
Dsram.S28 mov r3, #IO_ADDRESS(ARM_CKCTL) & 0xff000000
29 orr r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
30 orr r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
Dclock.c223 dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); in omap1_ckctl_recalc()
601 regval = omap_readw(ARM_CKCTL); in omap1_clk_set_rate()
605 omap_writew(regval, ARM_CKCTL); in omap1_clk_set_rate()
740 omap_readw(ARM_CKCTL)); in omap1_clk_init()
779 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL); in omap1_clk_init()
806 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); in omap1_clk_init()
808 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); in omap1_clk_init()
Dpm.c286 ARM_SAVE(ARM_CKCTL); in omap_pm_suspend()
309 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); in omap_pm_suspend()
377 ARM_RESTORE(ARM_CKCTL); in omap_pm_suspend()
446 ARM_SAVE(ARM_CKCTL); in omap_pm_read_proc()
504 ARM_SHOW(ARM_CKCTL), in omap_pm_read_proc()
Dclock.h303 .enable_reg = (void __iomem *)ARM_CKCTL,
/arch/arm/plat-omap/include/mach/
Dhardware.h73 #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) macro