Home
last modified time | relevance | path

Searched refs:A_BCM1480_IMR_CPU0_BASE (Results 1 – 2 of 2) sorted by relevance

/arch/mips/sibyte/bcm1480/
Dsmp.c39 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
46 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
53 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
/arch/mips/include/asm/sibyte/
Dbcm1480_regs.h367 #define A_BCM1480_IMR_CPU0_BASE 0x0010020000 macro
374 #define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING)
431 (A_BCM1480_IMR_CPU0_BASE + \