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Searched refs:A_BCM1480_IMR_CPU2_BASE (Results 1 – 2 of 2) sorted by relevance

/arch/mips/sibyte/bcm1480/
Dsmp.c41 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
48 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
55 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
/arch/mips/include/asm/sibyte/
Dbcm1480_regs.h369 #define A_BCM1480_IMR_CPU2_BASE 0x0010024000 macro