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Searched refs:A_IMR_CPU1_BASE (Results 1 – 2 of 2) sorted by relevance

/arch/mips/sibyte/sb1250/
Dsmp.c34 IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU)
39 IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU)
44 IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU)
/arch/mips/include/asm/sibyte/
Dsb1250_regs.h712 #define A_IMR_CPU1_BASE 0x0010022000 macro