1 /* 2 * arch/arm/mach-clps711x/include/mach/hardware.h 3 * 4 * This file contains the hardware definitions of the Prospector P720T. 5 * 6 * Copyright (C) 2000 Deep Blue Solutions Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 #ifndef __ASM_ARCH_HARDWARE_H 23 #define __ASM_ARCH_HARDWARE_H 24 25 26 #define CLPS7111_VIRT_BASE 0xff000000 27 #define CLPS7111_BASE CLPS7111_VIRT_BASE 28 29 /* 30 * The physical addresses that the external chip select signals map to is 31 * dependent on the setting of the nMEDCHG signal on EP7211 and EP7212 32 * processors. CONFIG_EP72XX_BOOT_ROM is only available if these 33 * processors are in use. 34 */ 35 #ifndef CONFIG_EP72XX_ROM_BOOT 36 #define CS0_PHYS_BASE (0x00000000) 37 #define CS1_PHYS_BASE (0x10000000) 38 #define CS2_PHYS_BASE (0x20000000) 39 #define CS3_PHYS_BASE (0x30000000) 40 #define CS4_PHYS_BASE (0x40000000) 41 #define CS5_PHYS_BASE (0x50000000) 42 #define CS6_PHYS_BASE (0x60000000) 43 #define CS7_PHYS_BASE (0x70000000) 44 #else 45 #define CS0_PHYS_BASE (0x70000000) 46 #define CS1_PHYS_BASE (0x60000000) 47 #define CS2_PHYS_BASE (0x50000000) 48 #define CS3_PHYS_BASE (0x40000000) 49 #define CS4_PHYS_BASE (0x30000000) 50 #define CS5_PHYS_BASE (0x20000000) 51 #define CS6_PHYS_BASE (0x10000000) 52 #define CS7_PHYS_BASE (0x00000000) 53 #endif 54 55 #if defined (CONFIG_ARCH_EP7211) 56 57 #define EP7211_VIRT_BASE CLPS7111_VIRT_BASE 58 #define EP7211_BASE CLPS7111_VIRT_BASE 59 #include <asm/hardware/ep7211.h> 60 61 #elif defined (CONFIG_ARCH_EP7212) 62 63 #define EP7212_VIRT_BASE CLPS7111_VIRT_BASE 64 #define EP7212_BASE CLPS7111_VIRT_BASE 65 #include <asm/hardware/ep7212.h> 66 67 #endif 68 69 #define SYSPLD_VIRT_BASE 0xfe000000 70 #define SYSPLD_BASE SYSPLD_VIRT_BASE 71 72 #ifndef __ASSEMBLER__ 73 74 #define PCIO_BASE IO_BASE 75 76 #endif 77 78 79 #if defined (CONFIG_ARCH_AUTCPU12) 80 81 #define CS89712_VIRT_BASE CLPS7111_VIRT_BASE 82 #define CS89712_BASE CLPS7111_VIRT_BASE 83 84 #include <asm/hardware/clps7111.h> 85 #include <asm/hardware/ep7212.h> 86 #include <asm/hardware/cs89712.h> 87 88 #endif 89 90 91 #if defined (CONFIG_ARCH_CDB89712) 92 93 #include <asm/hardware/clps7111.h> 94 #include <asm/hardware/ep7212.h> 95 #include <asm/hardware/cs89712.h> 96 97 /* static cdb89712_map_io() areas */ 98 #define REGISTER_START 0x80000000 99 #define REGISTER_SIZE 0x4000 100 #define REGISTER_BASE 0xff000000 101 102 #define ETHER_START 0x20000000 103 #define ETHER_SIZE 0x1000 104 #define ETHER_BASE 0xfe000000 105 106 #endif 107 108 109 #if defined (CONFIG_ARCH_EDB7211) 110 111 /* 112 * The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3) 113 * and repeat across it. This is the mapping for it. 114 * 115 * In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This 116 * was cause for much consternation and headscratching. This should probably 117 * be made a compile/run time kernel option. 118 */ 119 #define EP7211_PHYS_EXTKBD CS3_PHYS_BASE /* physical */ 120 121 #define EP7211_VIRT_EXTKBD (0xfd000000) /* virtual */ 122 123 124 /* 125 * The CS8900A ethernet chip has its I/O registers wired to chip select 2 126 * (nCS2). This is the mapping for it. 127 * 128 * In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This 129 * was cause for much consternation and headscratching. This should probably 130 * be made a compile/run time kernel option. 131 */ 132 #define EP7211_PHYS_CS8900A CS2_PHYS_BASE /* physical */ 133 134 #define EP7211_VIRT_CS8900A (0xfc000000) /* virtual */ 135 136 137 /* 138 * The two flash banks are wired to chip selects 0 and 1. This is the mapping 139 * for them. 140 * 141 * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running 142 * in jumpered boot mode. 143 */ 144 #define EP7211_PHYS_FLASH1 CS0_PHYS_BASE /* physical */ 145 #define EP7211_PHYS_FLASH2 CS1_PHYS_BASE /* physical */ 146 147 #define EP7211_VIRT_FLASH1 (0xfa000000) /* virtual */ 148 #define EP7211_VIRT_FLASH2 (0xfb000000) /* virtual */ 149 150 #endif /* CONFIG_ARCH_EDB7211 */ 151 152 153 /* 154 * Relevant bits in port D, which controls power to the various parts of 155 * the LCD on the EDB7211. 156 */ 157 #define EDB_PD1_LCD_DC_DC_EN (1<<1) 158 #define EDB_PD2_LCDEN (1<<2) 159 #define EDB_PD3_LCDBL (1<<3) 160 161 162 #if defined (CONFIG_ARCH_CEIVA) 163 164 #define CEIVA_VIRT_BASE CLPS7111_VIRT_BASE 165 #define CEIVA_BASE CLPS7111_VIRT_BASE 166 167 #include <asm/hardware/clps7111.h> 168 #include <asm/hardware/ep7212.h> 169 170 171 /* 172 * The two flash banks are wired to chip selects 0 and 1. This is the mapping 173 * for them. 174 * 175 * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running 176 * in jumpered boot mode. 177 */ 178 #define CEIVA_PHYS_FLASH1 CS0_PHYS_BASE /* physical */ 179 #define CEIVA_PHYS_FLASH2 CS1_PHYS_BASE /* physical */ 180 181 #define CEIVA_VIRT_FLASH1 (0xfa000000) /* virtual */ 182 #define CEIVA_VIRT_FLASH2 (0xfb000000) /* virtual */ 183 184 #define CEIVA_FLASH_SIZE 0x100000 185 #define CEIVA_FLASH_WIDTH 2 186 187 /* 188 * SED1355 LCD controller 189 */ 190 #define CEIVA_PHYS_SED1355 CS2_PHYS_BASE 191 #define CEIVA_VIRT_SED1355 (0xfc000000) 192 193 /* 194 * Relevant bits in port D, which controls power to the various parts of 195 * the LCD on the Ceiva Photo Max, and reset to the LCD controller. 196 */ 197 198 // Reset line to SED1355 (must be high to operate) 199 #define CEIVA_PD1_LCDRST (1<<1) 200 // LCD panel enable (set to one, to enable LCD) 201 #define CEIVA_PD4_LCDEN (1<<4) 202 // Backlight (set to one, to turn on backlight 203 #define CEIVA_PD5_LCDBL (1<<5) 204 205 /* 206 * Relevant bits in port B, which report the status of the buttons. 207 */ 208 209 // White button 210 #define CEIVA_PB4_WHT_BTN (1<<4) 211 // Black button 212 #define CEIVA_PB0_BLK_BTN (1<<0) 213 #endif // #if defined (CONFIG_ARCH_CEIVA) 214 215 #endif 216