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Searched refs:CL_2 (Results 1 – 8 of 8) sorted by relevance

/arch/blackfin/include/asm/
Dmem_init.h184 # define DDR_CL CL_2
/arch/blackfin/mach-bf533/include/mach/
DdefBF532.h1197 #define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ macro
/arch/blackfin/mach-bf561/include/mach/
DdefBF561.h1668 #define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ macro
/arch/blackfin/mach-bf518/include/mach/
DdefBF51x_base.h1329 #define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */ macro
/arch/blackfin/mach-bf527/include/mach/
DdefBF52x_base.h1338 #define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */ macro
/arch/blackfin/mach-bf537/include/mach/
DdefBF534.h1603 #define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles … macro
/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h1813 #define CL_2 0x20 /* DDR CAS Latency = 2 cycles */ macro
/arch/blackfin/mach-bf538/include/mach/
DdefBF539.h2463 #define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ macro