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Searched refs:CL_3 (Results 1 – 8 of 8) sorted by relevance

/arch/blackfin/include/asm/
Dmem_init.h97 #define SDRAM_CL CL_3
109 #define SDRAM_CL CL_3
/arch/blackfin/mach-bf533/include/mach/
DdefBF532.h1198 #define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ macro
/arch/blackfin/mach-bf561/include/mach/
DdefBF561.h1669 #define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ macro
/arch/blackfin/mach-bf518/include/mach/
DdefBF51x_base.h1330 #define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ macro
/arch/blackfin/mach-bf527/include/mach/
DdefBF52x_base.h1339 #define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ macro
/arch/blackfin/mach-bf537/include/mach/
DdefBF534.h1604 #define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles … macro
/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h1815 #define CL_3 0x30 /* DDR CAS Latency = 3 cycles */ macro
/arch/blackfin/mach-bf538/include/mach/
DdefBF539.h2464 #define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ macro