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Searched refs:CPLB_L1_AOW (Results 1 – 4 of 4) sorted by relevance

/arch/blackfin/include/asm/
Dcplb.h53 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
Ddef_LPBlackfin.h668 #define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on macro
/arch/blackfin/kernel/cplb-mpu/
Dcplbinit.c56 d_cache |= CPLB_L1_AOW | CPLB_WT; in generate_cplb_tables_cpu()
Dcplbmgr.c157 d_data |= CPLB_L1_AOW | CPLB_WT; in dcplb_miss()
372 d_data |= CPLB_L1_AOW | CPLB_WT; in set_mask_dcplbs()