Searched refs:CPLB_L1_CHBL (Results 1 – 4 of 4) sorted by relevance
35 #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)51 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)53 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)109 #define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT110 #define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY117 #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
653 #define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable macro
50 i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; in generate_cplb_tables_cpu()54 d_cache = CPLB_L1_CHBL; in generate_cplb_tables_cpu()
155 d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; in dcplb_miss()245 i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; in icplb_miss()370 d_data |= CPLB_L1_CHBL; in set_mask_dcplbs()