Searched refs:CPLB_VALID (Results 1 – 4 of 4) sorted by relevance
35 #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)37 #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)38 #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)48 #define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY…77 #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)112 #define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID113 #define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID114 #define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID116 #define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
635 #define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */ macro
116 if ((icplb_tbl[cpu][i].data & CPLB_VALID) == 0) in evict_one_icplb()131 if ((dcplb_tbl[cpu][i].data & CPLB_VALID) == 0) in evict_one_dcplb()152 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; in dcplb_miss()227 if (icplb_tbl[cpu][idx].data & CPLB_VALID) { in icplb_miss()236 i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB; in icplb_miss()368 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; in set_mask_dcplbs()
71 d_data = d_cache | CPLB_SUPV_WR | CPLB_VALID | PAGE_SIZE_4MB | CPLB_DIRTY; in generate_cplb_tables_cpu()72 i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB; in generate_cplb_tables_cpu()