Searched refs:DDR (Results 1 – 5 of 5) sorted by relevance
| /arch/arm/mach-omap2/ |
| D | sleep24xx.S | 89 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
109 movs r0, r0 @ see if DDR or SDR
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| D | sram243x.S | 143 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
177 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
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| D | sram242x.S | 143 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
177 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
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| /arch/xtensa/include/asm/ |
| D | regs.h | 46 #define DDR 104 macro
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| /arch/blackfin/ |
| D | Kconfig | 490 This sets the frequency of the system clock (including SDRAM or DDR).
495 prompt "DDR SDRAM Chip Type"
508 prompt "DDR/SDRAM Timing"
512 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
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