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Searched refs:DMA15_IRQ_STATUS (Results 1 – 4 of 4) sorted by relevance

/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h777 #define DMA15_IRQ_STATUS 0xffc01ce8 /* DMA Channel 15 Interrupt/Status Register … macro
DcdefBF54x_base.h1294 #define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
1295 #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
/arch/blackfin/mach-bf538/include/mach/
DdefBF539.h597 #define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */ macro
DcdefBF538.h930 #define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
931 #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)