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Searched refs:DMA3_START_ADDR (Results 1 – 12 of 12) sorted by relevance

/arch/blackfin/mach-bf533/include/mach/
DdefBF532.h275 #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ macro
DcdefBF532.h223 #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
224 #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
/arch/blackfin/mach-bf518/include/mach/
DdefBF51x_base.h293 #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ macro
DcdefBF51x_base.h518 #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
519 #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
/arch/blackfin/mach-bf527/include/mach/
DdefBF52x_base.h293 #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ macro
DcdefBF52x_base.h518 #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
519 #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
/arch/blackfin/mach-bf537/include/mach/
DdefBF534.h271 #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register … macro
DcdefBF534.h480 #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
481 #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h279 #define DMA3_START_ADDR 0xffc00cc4 /* DMA Channel 3 Start Address Register */ macro
DcdefBF54x_base.h424 #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
425 #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
/arch/blackfin/mach-bf538/include/mach/
DdefBF539.h290 #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ macro
DcdefBF538.h598 #define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
599 #define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)