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Searched refs:DMA5_CONFIG (Results 1 – 12 of 12) sorted by relevance

/arch/blackfin/mach-bf533/include/mach/
DdefBF532.h301 #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ macro
DcdefBF532.h273 #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
274 #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
/arch/blackfin/mach-bf518/include/mach/
DdefBF51x_base.h322 #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ macro
DcdefBF51x_base.h568 #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
569 #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
/arch/blackfin/mach-bf527/include/mach/
DdefBF52x_base.h322 #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ macro
DcdefBF52x_base.h568 #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
569 #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
/arch/blackfin/mach-bf537/include/mach/
DdefBF534.h300 #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register … macro
DcdefBF534.h530 #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
531 #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h312 #define DMA5_CONFIG 0xffc00d48 /* DMA Channel 5 Configuration Register */ macro
DcdefBF54x_base.h484 #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
485 #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
/arch/blackfin/mach-bf538/include/mach/
DdefBF539.h319 #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ macro
DcdefBF538.h652 #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
653 #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)