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Searched refs:EXCSAVE_1 (Results 1 – 7 of 7) sorted by relevance

/arch/xtensa/kernel/
Dvectors.S74 xsr a3, EXCSAVE_1 # save a3 and get dispatch table
98 xsr a3, EXCSAVE_1 # save a3, and get dispatch table
210 wsr a3, EXCSAVE_1 # save a3
259 wsr a3, EXCSAVE_1 # save a3
332 rsr a3, EXCSAVE_1
333 wsr a0, EXCSAVE_1
Dentry.S114 xsr a3, EXCSAVE_1
254 xsr a3, EXCSAVE_1 # restore a3, excsave_1
688 2: rsr a2, EXCSAVE_1
806 xsr a3, EXCSAVE_1 # make sure excsave_1 is valid for dbl.
822 wsr a0, EXCSAVE_1
991 rsr a3, EXCSAVE_1
993 wsr a0, EXCSAVE_1
1049 xsr a3, EXCSAVE_1 # restore a3, excsave1
1132 xsr a3, EXCSAVE_1 # restore a3 and excsave_1
1184 rsr a3, EXCSAVE_1 # get spill-mask
[all …]
Dcoprocessor.S46 wsr a0, EXCSAVE_1
223 wsr a0, EXCSAVE_1
232 xsr a3, EXCSAVE_1
Dhead.S67 wsr a2, EXCSAVE_1
219 xsr a6, EXCSAVE_1
Dalign.S174 xsr a3, EXCSAVE_1
409 rsr a3, EXCSAVE_1
Dtraps.c340 __asm__ __volatile__("wsr %0, "__stringify(EXCSAVE_1)"\n" : : "a" (i)); in trap_init()
/arch/xtensa/include/asm/
Dregs.h56 #define EXCSAVE_1 209 macro