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Searched refs:FPU_CSR_FLUSH (Results 1 – 2 of 2) sorted by relevance

/arch/mips/math-emu/
Dcp1emu.c383 value &= (FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03); in cop1Emulate()
384 ctx->fcr31 &= ~(FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03); in cop1Emulate()
/arch/mips/include/asm/
Dmipsregs.h126 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ macro