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Searched refs:GPIO (Results 1 – 25 of 90) sorted by relevance

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/arch/arm/mach-sa1100/include/mach/
Dh3600_gpio.h107 #define H3800_ASIC2_GPIO_Direction H3800_ASIC2_OFFSET( u16, GPIO, Direction )
108 #define H3800_ASIC2_GPIO_InterruptType H3800_ASIC2_OFFSET( u16, GPIO, InterruptType )
109 #define H3800_ASIC2_GPIO_InterruptEdgeType H3800_ASIC2_OFFSET( u16, GPIO, InterruptEdgeType )
110 #define H3800_ASIC2_GPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, GPIO, InterruptLevelType )
111 #define H3800_ASIC2_GPIO_InterruptClear H3800_ASIC2_OFFSET( u16, GPIO, InterruptClear )
112 #define H3800_ASIC2_GPIO_InterruptFlag H3800_ASIC2_OFFSET( u16, GPIO, InterruptFlag )
113 #define H3800_ASIC2_GPIO_Data H3800_ASIC2_OFFSET( u16, GPIO, Data )
114 #define H3800_ASIC2_GPIO_BattFaultOut H3800_ASIC2_OFFSET( u16, GPIO, BattFaultOut )
115 #define H3800_ASIC2_GPIO_InterruptEnable H3800_ASIC2_OFFSET( u16, GPIO, InterruptEnable )
116 #define H3800_ASIC2_GPIO_Alternate H3800_ASIC2_OFFSET( u16, GPIO, Alternate )
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/arch/arm/plat-s3c24xx/
DKconfig56 Add an extra 64 gpio numbers to the available GPIO pool. This is
62 Add an extra 128 gpio numbers to the available GPIO pool. This is
98 SPI GPIO configuration code for BUS0 when connected to
104 SPI GPIO configuration code for BUS 1 when connected to
Dcpu.c155 IODESC_ENT(GPIO),
/arch/arm/plat-s3c/
DKconfig115 Add a number of spare GPIO entries between each bank for debugging
129 Internal configuration to enable the correct GPIO pull helper
134 Internal configuration to enable the correct GPIO pull helper
139 Internal configuration to enable the correct GPIO pull helper
144 Internal configuration to enable S3C24XX style GPIO configuration
150 Internal configuration to enable S3C64XX style GPIO configuration
/arch/powerpc/platforms/pasemi/
DKconfig35 tristate "MDIO support via GPIO"
38 Driver for MDIO via GPIO on PWRficient platforms
/arch/powerpc/platforms/52xx/
DKconfig16 - GPIO pins are configured by the firmware,
48 bool "MPC5200 GPIO support"
/arch/sh/kernel/cpu/sh4a/
Dsetup-sh7780.c115 PCIC5, SCIF1, MMCIF, TMU345, FLCTL, GPIO, enumerator
168 INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
173 { 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
190 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
Dsetup-sh7785.c120 PCIC5, MMCIF, GDTA, TMU345, FLCTL, GPIO enumerator
178 INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
196 { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
217 { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
Dsetup-sh7763.c177 SCIF1, USBF, MMCIF, SIM, SCIF2, GPIO, enumerator
237 INTC_GROUP(GPIO, GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3),
242 { 0, 0, 0, 0, 0, 0, GPIO, 0,
264 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SCIF2, GPIO } },
/arch/powerpc/boot/dts/
Dpcm030.dts84 gpt2: timer@620 { /* General Purpose Timer in GPIO mode */
94 gpt3: timer@630 { /* General Purpose Timer in GPIO mode */
104 gpt4: timer@640 { /* General Purpose Timer in GPIO mode */
114 gpt5: timer@650 { /* General Purpose Timer in GPIO mode */
124 gpt6: timer@660 { /* General Purpose Timer in GPIO mode */
134 gpt7: timer@670 { /* General Purpose Timer in GPIO mode */
Dhcu4.dts114 GPIO: gpio@ef600700 { label
Dep405.dts124 GPIO: gpio@ef600700 { label
/arch/arm/mach-davinci/include/mach/
Dgpio.h43 #define GPIO(X) (X) /* 0 <= X <= 70 */ macro
/arch/powerpc/platforms/
DKconfig253 bool "QE GPIO support"
307 bool "MPC8xxx GPIO support"
316 bool "Support for simple, memory-mapped GPIO controllers"
321 Say Y here to support simple, memory-mapped GPIO controllers.
334 also register MCU GPIOs with the generic GPIO API, so you'll able
/arch/powerpc/platforms/8xx/
DKconfig115 bool "GPIO API Support"
120 with the GPIO API. If you say N here, the kernel needs less memory.
/arch/h8300/platform/h8s/edosk2674/
Dcrt0_rom.S32 ;BSC/GPIO setup
/arch/avr32/boards/atstk1000/
DKconfig75 GPIO lines and accessed through the J1 jumper block. Say "y"
/arch/arm/mach-s3c2410/
DKconfig34 GPIO code for S3C2410 and similar processors
/arch/frv/kernel/
Dsleep.S157 # Set the GPIO register so that the IRQ[3:0] pins become valid, as required.
338 # (5) Set the GPIO register so that the IRQ[3:0] pins become valid, as required.
/arch/mips/configs/
Djmr3927_defconfig607 # Memory mapped GPIO expanders:
611 # I2C GPIO expanders:
615 # PCI GPIO expanders:
620 # SPI GPIO expanders:
Drbtx49xx_defconfig694 # Memory mapped GPIO expanders:
698 # I2C GPIO expanders:
702 # PCI GPIO expanders:
707 # SPI GPIO expanders:
/arch/avr32/configs/
Datstk1004_defconfig405 # I2C GPIO expanders:
409 # PCI GPIO expanders:
413 # SPI GPIO expanders:
/arch/arm/configs/
Dpcm037_defconfig539 # GPIO Support
543 # I2C GPIO expanders:
547 # SPI GPIO expanders:
/arch/powerpc/platforms/40x/
DKconfig173 bool "PPC4xx GPIO support"
/arch/sh/configs/
Dmagicpanelr2_defconfig668 # Memory mapped GPIO expanders:
672 # I2C GPIO expanders:
676 # PCI GPIO expanders:
680 # SPI GPIO expanders:

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