1 /* 2 * Galileo/Marvell GT641xx IRQ definitions. 3 * 4 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 20 #ifndef _ASM_IRQ_GT641XX_H 21 #define _ASM_IRQ_GT641XX_H 22 23 #ifndef GT641XX_IRQ_BASE 24 #define GT641XX_IRQ_BASE 8 25 #endif 26 27 #define GT641XX_MEMORY_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 1) 28 #define GT641XX_DMA_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 2) 29 #define GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 3) 30 #define GT641XX_DMA0_IRQ (GT641XX_IRQ_BASE + 4) 31 #define GT641XX_DMA1_IRQ (GT641XX_IRQ_BASE + 5) 32 #define GT641XX_DMA2_IRQ (GT641XX_IRQ_BASE + 6) 33 #define GT641XX_DMA3_IRQ (GT641XX_IRQ_BASE + 7) 34 #define GT641XX_TIMER0_IRQ (GT641XX_IRQ_BASE + 8) 35 #define GT641XX_TIMER1_IRQ (GT641XX_IRQ_BASE + 9) 36 #define GT641XX_TIMER2_IRQ (GT641XX_IRQ_BASE + 10) 37 #define GT641XX_TIMER3_IRQ (GT641XX_IRQ_BASE + 11) 38 #define GT641XX_PCI_0_MASTER_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 12) 39 #define GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 13) 40 #define GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 14) 41 #define GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 15) 42 #define GT641XX_PCI_0_ADDRESS_ERROR_IRQ (GT641XX_IRQ_BASE + 16) 43 #define GT641XX_MEMORY_ERROR_IRQ (GT641XX_IRQ_BASE + 17) 44 #define GT641XX_PCI_0_MASTER_ABORT_IRQ (GT641XX_IRQ_BASE + 18) 45 #define GT641XX_PCI_0_TARGET_ABORT_IRQ (GT641XX_IRQ_BASE + 19) 46 #define GT641XX_PCI_0_RETRY_TIMEOUT_IRQ (GT641XX_IRQ_BASE + 20) 47 #define GT641XX_CPU_INT0_IRQ (GT641XX_IRQ_BASE + 21) 48 #define GT641XX_CPU_INT1_IRQ (GT641XX_IRQ_BASE + 22) 49 #define GT641XX_CPU_INT2_IRQ (GT641XX_IRQ_BASE + 23) 50 #define GT641XX_CPU_INT3_IRQ (GT641XX_IRQ_BASE + 24) 51 #define GT641XX_CPU_INT4_IRQ (GT641XX_IRQ_BASE + 25) 52 #define GT641XX_PCI_INT0_IRQ (GT641XX_IRQ_BASE + 26) 53 #define GT641XX_PCI_INT1_IRQ (GT641XX_IRQ_BASE + 27) 54 #define GT641XX_PCI_INT2_IRQ (GT641XX_IRQ_BASE + 28) 55 #define GT641XX_PCI_INT3_IRQ (GT641XX_IRQ_BASE + 29) 56 57 extern void gt641xx_irq_dispatch(void); 58 extern void gt641xx_irq_init(void); 59 60 #endif /* _ASM_IRQ_GT641XX_H */ 61