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Searched refs:GT_TC_CONTROL_ENTC0_MSK (Results 1 – 2 of 2) sorted by relevance

/arch/mips/kernel/
Dcevt-gt641xx.c42 GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK); in gt641xx_timer0_state()
55 ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK); in gt641xx_timer0_set_next_event()
56 ctrl |= GT_TC_CONTROL_ENTC0_MSK; in gt641xx_timer0_set_next_event()
74 ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK); in gt641xx_timer0_set_mode()
78 ctrl |= GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK; in gt641xx_timer0_set_mode()
81 ctrl |= GT_TC_CONTROL_ENTC0_MSK; in gt641xx_timer0_set_mode()
/arch/mips/include/asm/
Dgt64120.h457 #define GT_TC_CONTROL_ENTC0_MSK (MSK(1) << GT_TC_CONTROL_ENTC0_SHF) macro
458 #define GT_TC_CONTROL_ENTC0_BIT GT_TC_CONTROL_ENTC0_MSK