Searched refs:LR (Results 1 – 17 of 17) sorted by relevance
| /arch/powerpc/kernel/ |
| D | swsusp_asm64.S | 80 SAVE_SPECIAL(LR)
118 RESTORE_SPECIAL(LR)
225 RESTORE_SPECIAL(LR)
|
| /arch/arm/lib/ |
| D | backtrace.S | 71 bic sv_pc, sv_pc, mask @ mask PC/LR for the mode
81 bic r1, r1, mask @ mask PC/LR for the mode
|
| /arch/m32r/kernel/ |
| D | entry.S | 108 #define LR(reg) @(0x64,reg) macro
|
| /arch/powerpc/platforms/52xx/ |
| D | lite5200_sleep.S | 68 SAVE_SPRN(LR, 0x1c)
246 LOAD_SPRN(LR, 0x1c)
|
| /arch/m32r/platforms/oaks32r/ |
| D | dot.gdbinit.nommu | 81 printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
|
| /arch/powerpc/platforms/8xx/ |
| D | Kconfig | 145 (by not placing conditional branches or branches to LR or CTR
|
| /arch/m32r/platforms/mappi2/ |
| D | dot.gdbinit.vdec2 | 150 printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
|
| /arch/m32r/platforms/mappi3/ |
| D | dot.gdbinit | 139 printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
|
| /arch/m32r/platforms/m32700ut/ |
| D | dot.gdbinit_400MHz_32MB | 151 printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
|
| D | dot.gdbinit_200MHz_16MB | 151 printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
|
| D | dot.gdbinit_300MHz_32MB | 151 printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
|
| /arch/m32r/platforms/mappi/ |
| D | dot.gdbinit | 167 printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
|
| D | dot.gdbinit.nommu | 167 printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
|
| D | dot.gdbinit.smp | 235 printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$fp
|
| /arch/frv/kernel/ |
| D | switch_to.S | 115 # - SP, FP, LR, GR15, GR28 and GR29 will have been set up appropriately
|
| /arch/m32r/platforms/opsput/ |
| D | dot.gdbinit | 176 printf "R12[%08lx] FP[%08lx] LR[%08lx] SP[%08lx]\n",$r12,$fp,$lr,$sp
|
| /arch/arm/kernel/ |
| D | entry-armv.S | 471 subeq r4, r2, #4 @ ARM instr at LR - 4
472 subne r4, r2, #2 @ Thumb instr at LR - 2
|