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1 /*
2  *  arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
3  *
4  *  Taken from pxa-regs.h by Russell King
5  *
6  *  Author:	Nicolas Pitre
7  *  Copyright:	MontaVista Software Inc.
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13 
14 #ifndef __PXA2XX_REGS_H
15 #define __PXA2XX_REGS_H
16 
17 /*
18  * Memory controller
19  */
20 
21 #define MDCNFG		__REG(0x48000000)  /* SDRAM Configuration Register 0 */
22 #define MDREFR		__REG(0x48000004)  /* SDRAM Refresh Control Register */
23 #define MSC0		__REG(0x48000008)  /* Static Memory Control Register 0 */
24 #define MSC1		__REG(0x4800000C)  /* Static Memory Control Register 1 */
25 #define MSC2		__REG(0x48000010)  /* Static Memory Control Register 2 */
26 #define MECR		__REG(0x48000014)  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
27 #define SXLCR		__REG(0x48000018)  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
28 #define SXCNFG		__REG(0x4800001C)  /* Synchronous Static Memory Control Register */
29 #define SXMRS		__REG(0x48000024)  /* MRS value to be written to Synchronous Flash or SMROM */
30 #define MCMEM0		__REG(0x48000028)  /* Card interface Common Memory Space Socket 0 Timing */
31 #define MCMEM1		__REG(0x4800002C)  /* Card interface Common Memory Space Socket 1 Timing */
32 #define MCATT0		__REG(0x48000030)  /* Card interface Attribute Space Socket 0 Timing Configuration */
33 #define MCATT1		__REG(0x48000034)  /* Card interface Attribute Space Socket 1 Timing Configuration */
34 #define MCIO0		__REG(0x48000038)  /* Card interface I/O Space Socket 0 Timing Configuration */
35 #define MCIO1		__REG(0x4800003C)  /* Card interface I/O Space Socket 1 Timing Configuration */
36 #define MDMRS		__REG(0x48000040)  /* MRS value to be written to SDRAM */
37 #define BOOT_DEF	__REG(0x48000044)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
38 
39 /*
40  * More handy macros for PCMCIA
41  *
42  * Arg is socket number
43  */
44 #define MCMEM(s)	__REG2(0x48000028, (s)<<2 )  /* Card interface Common Memory Space Socket s Timing */
45 #define MCATT(s)	__REG2(0x48000030, (s)<<2 )  /* Card interface Attribute Space Socket s Timing Configuration */
46 #define MCIO(s)		__REG2(0x48000038, (s)<<2 )  /* Card interface I/O Space Socket s Timing Configuration */
47 
48 /* MECR register defines */
49 #define MECR_NOS	(1 << 0)	/* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
50 #define MECR_CIT	(1 << 1)	/* Card Is There: 0 -> no card, 1 -> card inserted */
51 
52 #define MDCNFG_DE0	(1 << 0)	/* SDRAM Bank 0 Enable */
53 #define MDCNFG_DE1	(1 << 1)	/* SDRAM Bank 1 Enable */
54 #define MDCNFG_DE2	(1 << 16)	/* SDRAM Bank 2 Enable */
55 #define MDCNFG_DE3	(1 << 17)	/* SDRAM Bank 3 Enable */
56 
57 #define MDREFR_K0DB4	(1 << 29)	/* SDCLK0 Divide by 4 Control/Status */
58 #define MDREFR_K2FREE	(1 << 25)	/* SDRAM Free-Running Control */
59 #define MDREFR_K1FREE	(1 << 24)	/* SDRAM Free-Running Control */
60 #define MDREFR_K0FREE	(1 << 23)	/* SDRAM Free-Running Control */
61 #define MDREFR_SLFRSH	(1 << 22)	/* SDRAM Self-Refresh Control/Status */
62 #define MDREFR_APD	(1 << 20)	/* SDRAM/SSRAM Auto-Power-Down Enable */
63 #define MDREFR_K2DB2	(1 << 19)	/* SDCLK2 Divide by 2 Control/Status */
64 #define MDREFR_K2RUN	(1 << 18)	/* SDCLK2 Run Control/Status */
65 #define MDREFR_K1DB2	(1 << 17)	/* SDCLK1 Divide by 2 Control/Status */
66 #define MDREFR_K1RUN	(1 << 16)	/* SDCLK1 Run Control/Status */
67 #define MDREFR_E1PIN	(1 << 15)	/* SDCKE1 Level Control/Status */
68 #define MDREFR_K0DB2	(1 << 14)	/* SDCLK0 Divide by 2 Control/Status */
69 #define MDREFR_K0RUN	(1 << 13)	/* SDCLK0 Run Control/Status */
70 #define MDREFR_E0PIN	(1 << 12)	/* SDCKE0 Level Control/Status */
71 
72 
73 #ifdef CONFIG_PXA27x
74 
75 #define ARB_CNTRL	__REG(0x48000048)  /* Arbiter Control Register */
76 
77 #define ARB_DMA_SLV_PARK	(1<<31)	   /* Be parked with DMA slave when idle */
78 #define ARB_CI_PARK		(1<<30)	   /* Be parked with Camera Interface when idle */
79 #define ARB_EX_MEM_PARK 	(1<<29)	   /* Be parked with external MEMC when idle */
80 #define ARB_INT_MEM_PARK	(1<<28)	   /* Be parked with internal MEMC when idle */
81 #define ARB_USB_PARK		(1<<27)	   /* Be parked with USB when idle */
82 #define ARB_LCD_PARK		(1<<26)	   /* Be parked with LCD when idle */
83 #define ARB_DMA_PARK		(1<<25)	   /* Be parked with DMA when idle */
84 #define ARB_CORE_PARK		(1<<24)	   /* Be parked with core when idle */
85 #define ARB_LOCK_FLAG		(1<<23)	   /* Only Locking masters gain access to the bus */
86 
87 #endif
88 
89 
90 /*
91  * Power Manager
92  */
93 
94 #define PMCR		__REG(0x40F00000)  /* Power Manager Control Register */
95 #define PSSR		__REG(0x40F00004)  /* Power Manager Sleep Status Register */
96 #define PSPR		__REG(0x40F00008)  /* Power Manager Scratch Pad Register */
97 #define PWER		__REG(0x40F0000C)  /* Power Manager Wake-up Enable Register */
98 #define PRER		__REG(0x40F00010)  /* Power Manager GPIO Rising-Edge Detect Enable Register */
99 #define PFER		__REG(0x40F00014)  /* Power Manager GPIO Falling-Edge Detect Enable Register */
100 #define PEDR		__REG(0x40F00018)  /* Power Manager GPIO Edge Detect Status Register */
101 #define PCFR		__REG(0x40F0001C)  /* Power Manager General Configuration Register */
102 #define PGSR0		__REG(0x40F00020)  /* Power Manager GPIO Sleep State Register for GP[31-0] */
103 #define PGSR1		__REG(0x40F00024)  /* Power Manager GPIO Sleep State Register for GP[63-32] */
104 #define PGSR2		__REG(0x40F00028)  /* Power Manager GPIO Sleep State Register for GP[84-64] */
105 #define PGSR3		__REG(0x40F0002C)  /* Power Manager GPIO Sleep State Register for GP[118-96] */
106 #define RCSR		__REG(0x40F00030)  /* Reset Controller Status Register */
107 
108 #define PSLR		__REG(0x40F00034)	/* Power Manager Sleep Config Register */
109 #define PSTR		__REG(0x40F00038)	/* Power Manager Standby Config Register */
110 #define PSNR		__REG(0x40F0003C)	/* Power Manager Sense Config Register */
111 #define PVCR		__REG(0x40F00040)	/* Power Manager VoltageControl Register */
112 #define PKWR		__REG(0x40F00050)	/* Power Manager KB Wake-up Enable Reg */
113 #define PKSR		__REG(0x40F00054)	/* Power Manager KB Level-Detect Register */
114 #define PCMD(x)	__REG2(0x40F00080, (x)<<2)
115 #define PCMD0	__REG(0x40F00080 + 0 * 4)
116 #define PCMD1	__REG(0x40F00080 + 1 * 4)
117 #define PCMD2	__REG(0x40F00080 + 2 * 4)
118 #define PCMD3	__REG(0x40F00080 + 3 * 4)
119 #define PCMD4	__REG(0x40F00080 + 4 * 4)
120 #define PCMD5	__REG(0x40F00080 + 5 * 4)
121 #define PCMD6	__REG(0x40F00080 + 6 * 4)
122 #define PCMD7	__REG(0x40F00080 + 7 * 4)
123 #define PCMD8	__REG(0x40F00080 + 8 * 4)
124 #define PCMD9	__REG(0x40F00080 + 9 * 4)
125 #define PCMD10	__REG(0x40F00080 + 10 * 4)
126 #define PCMD11	__REG(0x40F00080 + 11 * 4)
127 #define PCMD12	__REG(0x40F00080 + 12 * 4)
128 #define PCMD13	__REG(0x40F00080 + 13 * 4)
129 #define PCMD14	__REG(0x40F00080 + 14 * 4)
130 #define PCMD15	__REG(0x40F00080 + 15 * 4)
131 #define PCMD16	__REG(0x40F00080 + 16 * 4)
132 #define PCMD17	__REG(0x40F00080 + 17 * 4)
133 #define PCMD18	__REG(0x40F00080 + 18 * 4)
134 #define PCMD19	__REG(0x40F00080 + 19 * 4)
135 #define PCMD20	__REG(0x40F00080 + 20 * 4)
136 #define PCMD21	__REG(0x40F00080 + 21 * 4)
137 #define PCMD22	__REG(0x40F00080 + 22 * 4)
138 #define PCMD23	__REG(0x40F00080 + 23 * 4)
139 #define PCMD24	__REG(0x40F00080 + 24 * 4)
140 #define PCMD25	__REG(0x40F00080 + 25 * 4)
141 #define PCMD26	__REG(0x40F00080 + 26 * 4)
142 #define PCMD27	__REG(0x40F00080 + 27 * 4)
143 #define PCMD28	__REG(0x40F00080 + 28 * 4)
144 #define PCMD29	__REG(0x40F00080 + 29 * 4)
145 #define PCMD30	__REG(0x40F00080 + 30 * 4)
146 #define PCMD31	__REG(0x40F00080 + 31 * 4)
147 
148 #define PCMD_MBC	(1<<12)
149 #define PCMD_DCE	(1<<11)
150 #define PCMD_LC	(1<<10)
151 /* FIXME:  PCMD_SQC need be checked.   */
152 #define PCMD_SQC	(3<<8)	/* currently only bit 8 is changeable,
153 				   bit 9 should be 0 all day. */
154 #define PVCR_VCSA	(0x1<<14)
155 #define PVCR_CommandDelay (0xf80)
156 #define PCFR_PI2C_EN	(0x1 << 6)
157 
158 #define PSSR_OTGPH	(1 << 6)	/* OTG Peripheral control Hold */
159 #define PSSR_RDH	(1 << 5)	/* Read Disable Hold */
160 #define PSSR_PH		(1 << 4)	/* Peripheral Control Hold */
161 #define PSSR_STS	(1 << 3)	/* Standby Mode Status */
162 #define PSSR_VFS	(1 << 2)	/* VDD Fault Status */
163 #define PSSR_BFS	(1 << 1)	/* Battery Fault Status */
164 #define PSSR_SSS	(1 << 0)	/* Software Sleep Status */
165 
166 #define PSLR_SL_ROD	(1 << 20)	/* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
167 
168 #define PCFR_RO		(1 << 15)	/* RDH Override */
169 #define PCFR_PO		(1 << 14)	/* PH Override */
170 #define PCFR_GPROD	(1 << 12)	/* GPIO nRESET_OUT Disable */
171 #define PCFR_L1_EN	(1 << 11)	/* Sleep Mode L1 converter Enable */
172 #define PCFR_FVC	(1 << 10)	/* Frequency/Voltage Change */
173 #define PCFR_DC_EN	(1 << 7)	/* Sleep/deep-sleep DC-DC Converter Enable */
174 #define PCFR_PI2CEN	(1 << 6)	/* Enable PI2C controller */
175 #define PCFR_GPR_EN	(1 << 4)	/* nRESET_GPIO Pin Enable */
176 #define PCFR_DS		(1 << 3)	/* Deep Sleep Mode */
177 #define PCFR_FS		(1 << 2)	/* Float Static Chip Selects */
178 #define PCFR_FP		(1 << 1)	/* Float PCMCIA controls */
179 #define PCFR_OPDE	(1 << 0)	/* 3.6864 MHz oscillator power-down enable */
180 
181 #define RCSR_GPR	(1 << 3)	/* GPIO Reset */
182 #define RCSR_SMR	(1 << 2)	/* Sleep Mode */
183 #define RCSR_WDR	(1 << 1)	/* Watchdog Reset */
184 #define RCSR_HWR	(1 << 0)	/* Hardware Reset */
185 
186 #define PWER_GPIO(Nb)	(1 << Nb)	/* GPIO [0..15] wake-up enable     */
187 #define PWER_GPIO0	PWER_GPIO (0)	/* GPIO  [0] wake-up enable        */
188 #define PWER_GPIO1	PWER_GPIO (1)	/* GPIO  [1] wake-up enable        */
189 #define PWER_GPIO2	PWER_GPIO (2)	/* GPIO  [2] wake-up enable        */
190 #define PWER_GPIO3	PWER_GPIO (3)	/* GPIO  [3] wake-up enable        */
191 #define PWER_GPIO4	PWER_GPIO (4)	/* GPIO  [4] wake-up enable        */
192 #define PWER_GPIO5	PWER_GPIO (5)	/* GPIO  [5] wake-up enable        */
193 #define PWER_GPIO6	PWER_GPIO (6)	/* GPIO  [6] wake-up enable        */
194 #define PWER_GPIO7	PWER_GPIO (7)	/* GPIO  [7] wake-up enable        */
195 #define PWER_GPIO8	PWER_GPIO (8)	/* GPIO  [8] wake-up enable        */
196 #define PWER_GPIO9	PWER_GPIO (9)	/* GPIO  [9] wake-up enable        */
197 #define PWER_GPIO10	PWER_GPIO (10)	/* GPIO [10] wake-up enable        */
198 #define PWER_GPIO11	PWER_GPIO (11)	/* GPIO [11] wake-up enable        */
199 #define PWER_GPIO12	PWER_GPIO (12)	/* GPIO [12] wake-up enable        */
200 #define PWER_GPIO13	PWER_GPIO (13)	/* GPIO [13] wake-up enable        */
201 #define PWER_GPIO14	PWER_GPIO (14)	/* GPIO [14] wake-up enable        */
202 #define PWER_GPIO15	PWER_GPIO (15)	/* GPIO [15] wake-up enable        */
203 #define PWER_RTC	0x80000000	/* RTC alarm wake-up enable        */
204 
205 /*
206  * PXA2xx specific Core clock definitions
207  */
208 #define CCCR		__REG(0x41300000)  /* Core Clock Configuration Register */
209 #define CCSR		__REG(0x4130000C)  /* Core Clock Status Register */
210 #define CKEN		__REG(0x41300004)  /* Clock Enable Register */
211 #define OSCC		__REG(0x41300008)  /* Oscillator Configuration Register */
212 
213 #define CCCR_N_MASK	0x0380	/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
214 #define CCCR_M_MASK	0x0060	/* Memory Frequency to Run Mode Frequency Multiplier */
215 #define CCCR_L_MASK	0x001f	/* Crystal Frequency to Memory Frequency Multiplier */
216 
217 #define CKEN_AC97CONF   (31)    /* AC97 Controller Configuration */
218 #define CKEN_CAMERA	(24)	/* Camera Interface Clock Enable */
219 #define CKEN_SSP1	(23)	/* SSP1 Unit Clock Enable */
220 #define CKEN_MEMC	(22)	/* Memory Controller Clock Enable */
221 #define CKEN_MEMSTK	(21)	/* Memory Stick Host Controller */
222 #define CKEN_IM		(20)	/* Internal Memory Clock Enable */
223 #define CKEN_KEYPAD	(19)	/* Keypad Interface Clock Enable */
224 #define CKEN_USIM	(18)	/* USIM Unit Clock Enable */
225 #define CKEN_MSL	(17)	/* MSL Unit Clock Enable */
226 #define CKEN_LCD	(16)	/* LCD Unit Clock Enable */
227 #define CKEN_PWRI2C	(15)	/* PWR I2C Unit Clock Enable */
228 #define CKEN_I2C	(14)	/* I2C Unit Clock Enable */
229 #define CKEN_FICP	(13)	/* FICP Unit Clock Enable */
230 #define CKEN_MMC	(12)	/* MMC Unit Clock Enable */
231 #define CKEN_USB	(11)	/* USB Unit Clock Enable */
232 #define CKEN_ASSP	(10)	/* ASSP (SSP3) Clock Enable */
233 #define CKEN_USBHOST	(10)	/* USB Host Unit Clock Enable */
234 #define CKEN_OSTIMER	(9)	/* OS Timer Unit Clock Enable */
235 #define CKEN_NSSP	(9)	/* NSSP (SSP2) Clock Enable */
236 #define CKEN_I2S	(8)	/* I2S Unit Clock Enable */
237 #define CKEN_BTUART	(7)	/* BTUART Unit Clock Enable */
238 #define CKEN_FFUART	(6)	/* FFUART Unit Clock Enable */
239 #define CKEN_STUART	(5)	/* STUART Unit Clock Enable */
240 #define CKEN_HWUART	(4)	/* HWUART Unit Clock Enable */
241 #define CKEN_SSP3	(4)	/* SSP3 Unit Clock Enable */
242 #define CKEN_SSP	(3)	/* SSP Unit Clock Enable */
243 #define CKEN_SSP2	(3)	/* SSP2 Unit Clock Enable */
244 #define CKEN_AC97	(2)	/* AC97 Unit Clock Enable */
245 #define CKEN_PWM1	(1)	/* PWM1 Clock Enable */
246 #define CKEN_PWM0	(0)	/* PWM0 Clock Enable */
247 
248 #define OSCC_OON	(1 << 1)	/* 32.768kHz OON (write-once only bit) */
249 #define OSCC_OOK	(1 << 0)	/* 32.768kHz OOK (read-only bit) */
250 
251 /* PWRMODE register M field values */
252 
253 #define PWRMODE_IDLE		0x1
254 #define PWRMODE_STANDBY		0x2
255 #define PWRMODE_SLEEP		0x3
256 #define PWRMODE_DEEPSLEEP	0x7
257 
258 #endif
259