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Searched refs:PMCR (Results 1 – 12 of 12) sorted by relevance

/arch/sh/oprofile/
Dop_model_sh7750.c25 #define PMCR(n) (PM_CR_BASE + ((n) * 0x04)) macro
156 __raw_writew(__raw_readw(PMCR(counter)) | PMCR_PMCLR, PMCR(counter)); in sh7750_write_count()
196 __raw_writew(0, PMCR(i)); in sh7750_ppc_cpu_setup()
208 __raw_writew(regcache[i].ctrl, PMCR(i)); in sh7750_ppc_cpu_start()
218 __raw_writew(__raw_readw(PMCR(i)) & ~PMCR_PMEN, PMCR(i)); in sh7750_ppc_cpu_stop()
228 __raw_writew(__raw_readw(PMCR(i)) | PMCR_PMCLR, PMCR(i)); in sh7750_ppc_reset()
/arch/arm/oprofile/
Dop_model_mpcore.c88 writel(1 << (cnt + 16), &emc->PMCR); in scu_em_interrupt()
134 temp = readl(&emc->PMCR); in scu_start()
150 writel(temp, &emc->PMCR); in scu_start()
167 temp = readl(&emc->PMCR); in scu_stop()
172 writel(temp, &emc->PMCR); in scu_stop()
Dop_model_mpcore.h20 unsigned long PMCR; member
/arch/arm/mach-sa1100/
Dsleep.S130 ldr r12, =PMCR
159 @ Step 6 set force sleep bit in PMCR
Dsimpad.c190 PMCR = PMCR_SF; in simpad_power_off()
Dgeneric.c162 PMCR = PMCR_SF; in sa1100_power_off()
/arch/arm/mach-pxa/include/mach/
Dpxa3xx-regs.h27 #define PMCR __REG(0x40F50000) /* Power Manager Control Register */ macro
Dpxa2xx-regs.h94 #define PMCR __REG(0x40F00000) /* Power Manager Control Register */ macro
/arch/arm/mach-pxa/
Dcm-x2xx.c401 PMCR = 0x00000005; in cmx2xx_suspend()
Dspitz.c732 PMCR = 0x00; in common_init()
Dtosa.c907 PMCR = 0x01; in tosa_init()
/arch/arm/mach-sa1100/include/mach/
DSA-1100.h917 #define PMCR __REG(0x90020000) /* PM Control Reg. */ macro