1 #ifndef _ASM_POWERPC_MMU_44X_H_ 2 #define _ASM_POWERPC_MMU_44X_H_ 3 /* 4 * PPC440 support 5 */ 6 7 #include <asm/page.h> 8 9 #define PPC44x_MMUCR_TID 0x000000ff 10 #define PPC44x_MMUCR_STS 0x00010000 11 12 #define PPC44x_TLB_PAGEID 0 13 #define PPC44x_TLB_XLAT 1 14 #define PPC44x_TLB_ATTRIB 2 15 16 /* Page identification fields */ 17 #define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */ 18 #define PPC44x_TLB_VALID 0x00000200 /* Valid flag */ 19 #define PPC44x_TLB_TS 0x00000100 /* Translation address space */ 20 #define PPC44x_TLB_1K 0x00000000 /* Page sizes */ 21 #define PPC44x_TLB_4K 0x00000010 22 #define PPC44x_TLB_16K 0x00000020 23 #define PPC44x_TLB_64K 0x00000030 24 #define PPC44x_TLB_256K 0x00000040 25 #define PPC44x_TLB_1M 0x00000050 26 #define PPC44x_TLB_16M 0x00000070 27 #define PPC44x_TLB_256M 0x00000090 28 29 /* Translation fields */ 30 #define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */ 31 #define PPC44x_TLB_ERPN_MASK 0x0000000f 32 33 /* Storage attribute and access control fields */ 34 #define PPC44x_TLB_ATTR_MASK 0x0000ff80 35 #define PPC44x_TLB_U0 0x00008000 /* User 0 */ 36 #define PPC44x_TLB_U1 0x00004000 /* User 1 */ 37 #define PPC44x_TLB_U2 0x00002000 /* User 2 */ 38 #define PPC44x_TLB_U3 0x00001000 /* User 3 */ 39 #define PPC44x_TLB_W 0x00000800 /* Caching is write-through */ 40 #define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */ 41 #define PPC44x_TLB_M 0x00000200 /* Memory is coherent */ 42 #define PPC44x_TLB_G 0x00000100 /* Memory is guarded */ 43 #define PPC44x_TLB_E 0x00000080 /* Memory is guarded */ 44 45 #define PPC44x_TLB_PERM_MASK 0x0000003f 46 #define PPC44x_TLB_UX 0x00000020 /* User execution */ 47 #define PPC44x_TLB_UW 0x00000010 /* User write */ 48 #define PPC44x_TLB_UR 0x00000008 /* User read */ 49 #define PPC44x_TLB_SX 0x00000004 /* Super execution */ 50 #define PPC44x_TLB_SW 0x00000002 /* Super write */ 51 #define PPC44x_TLB_SR 0x00000001 /* Super read */ 52 53 /* Number of TLB entries */ 54 #define PPC44x_TLB_SIZE 64 55 56 #ifndef __ASSEMBLY__ 57 58 extern unsigned int tlb_44x_hwater; 59 extern unsigned int tlb_44x_index; 60 61 typedef struct { 62 unsigned int id; 63 unsigned int active; 64 unsigned long vdso_base; 65 } mm_context_t; 66 67 #endif /* !__ASSEMBLY__ */ 68 69 #ifndef CONFIG_PPC_EARLY_DEBUG_44x 70 #define PPC44x_EARLY_TLBS 1 71 #else 72 #define PPC44x_EARLY_TLBS 2 73 #define PPC44x_EARLY_DEBUG_VIRTADDR (ASM_CONST(0xf0000000) \ 74 | (ASM_CONST(CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW) & 0xffff)) 75 #endif 76 77 /* Size of the TLBs used for pinning in lowmem */ 78 #define PPC_PIN_SIZE (1 << 28) /* 256M */ 79 80 #if (PAGE_SHIFT == 12) 81 #define PPC44x_TLBE_SIZE PPC44x_TLB_4K 82 #elif (PAGE_SHIFT == 14) 83 #define PPC44x_TLBE_SIZE PPC44x_TLB_16K 84 #elif (PAGE_SHIFT == 16) 85 #define PPC44x_TLBE_SIZE PPC44x_TLB_64K 86 #else 87 #error "Unsupported PAGE_SIZE" 88 #endif 89 90 #define PPC44x_PGD_OFF_SHIFT (32 - PGDIR_SHIFT + PGD_T_LOG2) 91 #define PPC44x_PGD_OFF_MASK_BIT (PGDIR_SHIFT - PGD_T_LOG2) 92 #define PPC44x_PTE_ADD_SHIFT (32 - PGDIR_SHIFT + PTE_SHIFT + PTE_T_LOG2) 93 #define PPC44x_PTE_ADD_MASK_BIT (32 - PTE_T_LOG2 - PTE_SHIFT) 94 95 #endif /* _ASM_POWERPC_MMU_44X_H_ */ 96