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Searched refs:REG (Results 1 – 20 of 20) sorted by relevance

/arch/m68knommu/lib/
Dmulsi3.S66 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
72 #define d0 REG (d0)
73 #define d1 REG (d1)
74 #define d2 REG (d2)
75 #define d3 REG (d3)
76 #define d4 REG (d4)
77 #define d5 REG (d5)
78 #define d6 REG (d6)
79 #define d7 REG (d7)
80 #define a0 REG (a0)
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Dumodsi3.S66 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
72 #define d0 REG (d0)
73 #define d1 REG (d1)
74 #define d2 REG (d2)
75 #define d3 REG (d3)
76 #define d4 REG (d4)
77 #define d5 REG (d5)
78 #define d6 REG (d6)
79 #define d7 REG (d7)
80 #define a0 REG (a0)
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Dmodsi3.S66 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
72 #define d0 REG (d0)
73 #define d1 REG (d1)
74 #define d2 REG (d2)
75 #define d3 REG (d3)
76 #define d4 REG (d4)
77 #define d5 REG (d5)
78 #define d6 REG (d6)
79 #define d7 REG (d7)
80 #define a0 REG (a0)
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Ddivsi3.S66 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
72 #define d0 REG (d0)
73 #define d1 REG (d1)
74 #define d2 REG (d2)
75 #define d3 REG (d3)
76 #define d4 REG (d4)
77 #define d5 REG (d5)
78 #define d6 REG (d6)
79 #define d7 REG (d7)
80 #define a0 REG (a0)
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Dudivsi3.S66 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
72 #define d0 REG (d0)
73 #define d1 REG (d1)
74 #define d2 REG (d2)
75 #define d3 REG (d3)
76 #define d4 REG (d4)
77 #define d5 REG (d5)
78 #define d6 REG (d6)
79 #define d7 REG (d7)
80 #define a0 REG (a0)
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/arch/sparc/include/asm/
Dasm.h13 #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ argument
14 brz,PREDICT REG, DEST
15 #define BRANCH_REG_ZERO_ANNUL(PREDICT, REG, DEST) \ argument
16 brz,a,PREDICT REG, DEST
17 #define BRANCH_REG_NOT_ZERO(PREDICT, REG, DEST) \ argument
18 brnz,PREDICT REG, DEST
19 #define BRANCH_REG_NOT_ZERO_ANNUL(PREDICT, REG, DEST) \ argument
20 brnz,a,PREDICT REG, DEST
26 #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ argument
27 cmp REG, 0; \
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Dcpudata_64.h141 #define __GET_CPUID(REG) \ argument
143 661: ldxa [%g0] ASI_UPA_CONFIG, REG; \
144 srlx REG, 17, REG; \
145 and REG, 0x1f, REG; \
151 ldxa [%g0] ASI_SAFARI_CONFIG, REG; \
152 srlx REG, 17, REG; \
153 and REG, 0x3ff, REG; \
156 ldxa [%g0] ASI_JBUS_CONFIG, REG; \
157 srlx REG, 17, REG; \
158 and REG, 0x1f, REG; \
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Dtsb.h76 #define TSB_LOAD_QUAD(TSB, REG) \ argument
77 661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
80 ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
81 ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
84 #define TSB_LOAD_TAG_HIGH(TSB, REG) \ argument
85 661: lduwa [TSB] ASI_N, REG; \
88 lduwa [TSB] ASI_PHYS_USE_EC, REG; \
91 #define TSB_LOAD_TAG(TSB, REG) \ argument
92 661: ldxa [TSB] ASI_N, REG; \
95 ldxa [TSB] ASI_PHYS_USE_EC, REG; \
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/arch/arm/mach-netx/include/mach/
Duncompress.h29 #define REG(x) (*(volatile unsigned long *)(x)) macro
47 if (REG(UART1_BASE + UART_CR) & CR_UART_EN) in putc()
49 else if (REG(UART2_BASE + UART_CR) & CR_UART_EN) in putc()
54 while (REG(base + UART_FR) & FR_TXFF); in putc()
55 REG(base + UART_DR) = c; in putc()
62 if (REG(UART1_BASE + UART_CR) & CR_UART_EN) in flush()
64 else if (REG(UART2_BASE + UART_CR) & CR_UART_EN) in flush()
69 while (REG(base + UART_FR) & FR_BUSY); in flush()
/arch/sparc/kernel/
Dpsycho_common.h14 #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \ argument
17 ((unsigned long)(REG)))
Dprom_irqtrans.c101 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \ argument
104 ((unsigned long)(REG)))
Dpci_schizo.c72 #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \ argument
75 ((unsigned long)(REG)))
/arch/powerpc/kernel/
Dprocess.c492 #define REG "%016lx" macro
496 #define REG "%08lx" macro
505 printk("NIP: "REG" LR: "REG" CTR: "REG"\n", in show_regs()
509 printk("MSR: "REG" ", regs->msr); in show_regs()
515 printk("DEAR: "REG", ESR: "REG"\n", regs->dar, regs->dsisr); in show_regs()
517 printk("DAR: "REG", DSISR: "REG"\n", regs->dar, regs->dsisr); in show_regs()
529 printk(REG " ", regs->gpr[i]); in show_regs()
539 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); in show_regs()
540 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); in show_regs()
1032 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); in show_stack()
/arch/powerpc/xmon/
Dxmon.c164 #define REG "%.16lx" macro
168 #define REG "%.8lx" macro
1172 printf(" data "REG" [", dabr.address); in bpt_cmds()
1308 printf("["REG"] ", sp); in xmon_show_stack()
1314 printf("["REG"] ", sp); in xmon_show_stack()
1432 printf("*** Error reading registers from "REG"\n", in prregs()
1443 printf("R%.2ld = "REG" R%.2ld = "REG"\n", in prregs()
1447 printf("R%.2ld = "REG" R%.2ld = "REG"\n", in prregs()
1464 printf("msr = "REG" cr = %.8lx\n", fp->msr, fp->ccr); in prregs()
1465 printf("ctr = "REG" xer = "REG" trap = %4lx\n", in prregs()
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/arch/powerpc/include/asm/
Dreg.h621 #define MTFSF_L(REG) \ argument
622 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
624 #define MTFSF_L(REG) mtfsf 0xff, (REG) argument
/arch/mips/mti-malta/
Dmalta-int.c445 gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & in arch_init_irq()
538 i = REG(_msc01_biu_base, MSC01_SC_CFG); in arch_init_irq()
539 REG(_msc01_biu_base, MSC01_SC_CFG) = in arch_init_irq()
/arch/mips/include/asm/
Dgic.h27 #define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS) macro
/arch/m68k/ifpsp060/src/
Disp.S916 # MODE and REG are taken from the EXC_OPWORD.
923 # jump to the corresponding function for each {MODE,REG} pair.
Dpfpsp.S4575 # currently, MODE and REG are taken from the EXC_OPWORD. this could be
4583 # jump to the corresponding function for each {MODE,REG} pair.
Dfpsp.S18526 # currently, MODE and REG are taken from the EXC_OPWORD. this could be
18534 # jump to the corresponding function for each {MODE,REG} pair.