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Searched refs:REG2 (Results 1 – 4 of 4) sorted by relevance

/arch/sparc/include/asm/
Dtsb.h98 #define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \ argument
99 661: casa [TSB] ASI_N, REG1, REG2; \
102 casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
105 #define TSB_CAS_TAG(TSB, REG1, REG2) \ argument
106 661: casxa [TSB] ASI_N, REG1, REG2; \
109 casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
119 #define TSB_LOCK_TAG(TSB, REG1, REG2) \ argument
121 sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
122 andcc REG1, REG2, %g0; \
125 TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \
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Dcpudata_64.h205 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \ argument
208 sethi %hi(__per_cpu_base), REG2; \
210 ldx [REG2 + %lo(__per_cpu_base)], REG2; \
212 add REG3, REG2, DEST;
235 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) argument
/arch/m32r/kernel/
Dalign.c39 #define REG2(insn) ((insn) & 0x000f) macro
106 int src = REG2(insn); in emu_add()
124 val += (unsigned int)get_reg(regs, REG2(insn)); in emu_addx()
142 val &= get_reg(regs, REG2(insn)); in emu_and()
150 if (get_reg(regs, REG1(insn)) < get_reg(regs, REG2(insn))) in emu_cmp()
160 if (get_reg(regs, REG1(insn)) == get_reg(regs, REG2(insn))) in emu_cmpeq()
171 < (unsigned int)get_reg(regs, REG2(insn))) in emu_cmpu()
181 if (!get_reg(regs, REG2(insn))) in emu_cmpz()
193 val = get_reg(regs, REG2(insn)); in emu_mv()
203 val = get_reg(regs, REG2(insn)); in emu_neg()
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/arch/sparc/kernel/
Dsys32.S22 #define SIGN2(STUB,SYSCALL,REG1,REG2) \ argument
28 sra REG2, 0, REG2
30 #define SIGN3(STUB,SYSCALL,REG1,REG2,REG3) \ argument
35 sra REG2, 0, REG2; \
39 #define SIGN4(STUB,SYSCALL,REG1,REG2,REG3,REG4) \ argument
44 sra REG2, 0, REG2; \