1 #ifndef __ddr2_defs_h 2 #define __ddr2_defs_h 3 4 /* 5 * This file is autogenerated from 6 * file: ddr2.r 7 * 8 * by ../../../tools/rdesc/bin/rdes2c -outfile ddr2_defs.h ddr2.r 9 * Any changes here will be lost. 10 * 11 * -*- buffer-read-only: t -*- 12 */ 13 /* Main access macros */ 14 #ifndef REG_RD 15 #define REG_RD( scope, inst, reg ) \ 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 18 #endif 19 20 #ifndef REG_WR 21 #define REG_WR( scope, inst, reg, val ) \ 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 24 #endif 25 26 #ifndef REG_RD_VECT 27 #define REG_RD_VECT( scope, inst, reg, index ) \ 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) 31 #endif 32 33 #ifndef REG_WR_VECT 34 #define REG_WR_VECT( scope, inst, reg, index, val ) \ 35 REG_WRITE( reg_##scope##_##reg, \ 36 (inst) + REG_WR_ADDR_##scope##_##reg + \ 37 (index) * STRIDE_##scope##_##reg, (val) ) 38 #endif 39 40 #ifndef REG_RD_INT 41 #define REG_RD_INT( scope, inst, reg ) \ 42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) 43 #endif 44 45 #ifndef REG_WR_INT 46 #define REG_WR_INT( scope, inst, reg, val ) \ 47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 48 #endif 49 50 #ifndef REG_RD_INT_VECT 51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ 52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ 53 (index) * STRIDE_##scope##_##reg ) 54 #endif 55 56 #ifndef REG_WR_INT_VECT 57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ 58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ 59 (index) * STRIDE_##scope##_##reg, (val) ) 60 #endif 61 62 #ifndef REG_TYPE_CONV 63 #define REG_TYPE_CONV( type, orgtype, val ) \ 64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) 65 #endif 66 67 #ifndef reg_page_size 68 #define reg_page_size 8192 69 #endif 70 71 #ifndef REG_ADDR 72 #define REG_ADDR( scope, inst, reg ) \ 73 ( (inst) + REG_RD_ADDR_##scope##_##reg ) 74 #endif 75 76 #ifndef REG_ADDR_VECT 77 #define REG_ADDR_VECT( scope, inst, reg, index ) \ 78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \ 79 (index) * STRIDE_##scope##_##reg ) 80 #endif 81 82 /* C-code for register scope ddr2 */ 83 84 /* Register rw_cfg, scope ddr2, type rw */ 85 typedef struct { 86 unsigned int col_width : 4; 87 unsigned int nr_banks : 1; 88 unsigned int bw : 1; 89 unsigned int nr_ref : 4; 90 unsigned int ref_interval : 11; 91 unsigned int odt_ctrl : 2; 92 unsigned int odt_mem : 1; 93 unsigned int imp_strength : 1; 94 unsigned int auto_imp_cal : 1; 95 unsigned int imp_cal_override : 1; 96 unsigned int dll_override : 1; 97 unsigned int dummy1 : 4; 98 } reg_ddr2_rw_cfg; 99 #define REG_RD_ADDR_ddr2_rw_cfg 0 100 #define REG_WR_ADDR_ddr2_rw_cfg 0 101 102 /* Register rw_timing, scope ddr2, type rw */ 103 typedef struct { 104 unsigned int wr : 3; 105 unsigned int rcd : 3; 106 unsigned int rp : 3; 107 unsigned int ras : 4; 108 unsigned int rfc : 7; 109 unsigned int rc : 5; 110 unsigned int rtp : 2; 111 unsigned int rtw : 3; 112 unsigned int wtr : 2; 113 } reg_ddr2_rw_timing; 114 #define REG_RD_ADDR_ddr2_rw_timing 4 115 #define REG_WR_ADDR_ddr2_rw_timing 4 116 117 /* Register rw_latency, scope ddr2, type rw */ 118 typedef struct { 119 unsigned int cas : 3; 120 unsigned int additive : 3; 121 unsigned int dummy1 : 26; 122 } reg_ddr2_rw_latency; 123 #define REG_RD_ADDR_ddr2_rw_latency 8 124 #define REG_WR_ADDR_ddr2_rw_latency 8 125 126 /* Register rw_phy_cfg, scope ddr2, type rw */ 127 typedef struct { 128 unsigned int en : 1; 129 unsigned int dummy1 : 31; 130 } reg_ddr2_rw_phy_cfg; 131 #define REG_RD_ADDR_ddr2_rw_phy_cfg 12 132 #define REG_WR_ADDR_ddr2_rw_phy_cfg 12 133 134 /* Register rw_phy_ctrl, scope ddr2, type rw */ 135 typedef struct { 136 unsigned int rst : 1; 137 unsigned int cal_rst : 1; 138 unsigned int cal_start : 1; 139 unsigned int dummy1 : 29; 140 } reg_ddr2_rw_phy_ctrl; 141 #define REG_RD_ADDR_ddr2_rw_phy_ctrl 16 142 #define REG_WR_ADDR_ddr2_rw_phy_ctrl 16 143 144 /* Register rw_ctrl, scope ddr2, type rw */ 145 typedef struct { 146 unsigned int mrs_data : 16; 147 unsigned int cmd : 8; 148 unsigned int dummy1 : 8; 149 } reg_ddr2_rw_ctrl; 150 #define REG_RD_ADDR_ddr2_rw_ctrl 20 151 #define REG_WR_ADDR_ddr2_rw_ctrl 20 152 153 /* Register rw_pwr_down, scope ddr2, type rw */ 154 typedef struct { 155 unsigned int self_ref : 2; 156 unsigned int phy_en : 1; 157 unsigned int dummy1 : 29; 158 } reg_ddr2_rw_pwr_down; 159 #define REG_RD_ADDR_ddr2_rw_pwr_down 24 160 #define REG_WR_ADDR_ddr2_rw_pwr_down 24 161 162 /* Register r_stat, scope ddr2, type r */ 163 typedef struct { 164 unsigned int dll_lock : 1; 165 unsigned int dll_delay_code : 7; 166 unsigned int imp_cal_done : 1; 167 unsigned int imp_cal_fault : 1; 168 unsigned int cal_imp_pu : 4; 169 unsigned int cal_imp_pd : 4; 170 unsigned int dummy1 : 14; 171 } reg_ddr2_r_stat; 172 #define REG_RD_ADDR_ddr2_r_stat 28 173 174 /* Register rw_imp_ctrl, scope ddr2, type rw */ 175 typedef struct { 176 unsigned int imp_pu : 4; 177 unsigned int imp_pd : 4; 178 unsigned int dummy1 : 24; 179 } reg_ddr2_rw_imp_ctrl; 180 #define REG_RD_ADDR_ddr2_rw_imp_ctrl 32 181 #define REG_WR_ADDR_ddr2_rw_imp_ctrl 32 182 183 #define STRIDE_ddr2_rw_dll_ctrl 4 184 /* Register rw_dll_ctrl, scope ddr2, type rw */ 185 typedef struct { 186 unsigned int mode : 1; 187 unsigned int clk_delay : 7; 188 unsigned int dummy1 : 24; 189 } reg_ddr2_rw_dll_ctrl; 190 #define REG_RD_ADDR_ddr2_rw_dll_ctrl 36 191 #define REG_WR_ADDR_ddr2_rw_dll_ctrl 36 192 193 #define STRIDE_ddr2_rw_dqs_dll_ctrl 4 194 /* Register rw_dqs_dll_ctrl, scope ddr2, type rw */ 195 typedef struct { 196 unsigned int dqs90_delay : 7; 197 unsigned int dqs180_delay : 7; 198 unsigned int dqs270_delay : 7; 199 unsigned int dqs360_delay : 7; 200 unsigned int dummy1 : 4; 201 } reg_ddr2_rw_dqs_dll_ctrl; 202 #define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52 203 #define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52 204 205 206 /* Constants */ 207 enum { 208 regk_ddr2_al0 = 0x00000000, 209 regk_ddr2_al1 = 0x00000008, 210 regk_ddr2_al2 = 0x00000010, 211 regk_ddr2_al3 = 0x00000018, 212 regk_ddr2_al4 = 0x00000020, 213 regk_ddr2_auto = 0x00000003, 214 regk_ddr2_bank4 = 0x00000000, 215 regk_ddr2_bank8 = 0x00000001, 216 regk_ddr2_bl4 = 0x00000002, 217 regk_ddr2_bl8 = 0x00000003, 218 regk_ddr2_bt_il = 0x00000008, 219 regk_ddr2_bt_seq = 0x00000000, 220 regk_ddr2_bw16 = 0x00000001, 221 regk_ddr2_bw32 = 0x00000000, 222 regk_ddr2_cas2 = 0x00000020, 223 regk_ddr2_cas3 = 0x00000030, 224 regk_ddr2_cas4 = 0x00000040, 225 regk_ddr2_cas5 = 0x00000050, 226 regk_ddr2_deselect = 0x000000c0, 227 regk_ddr2_dic_weak = 0x00000002, 228 regk_ddr2_direct = 0x00000001, 229 regk_ddr2_dis = 0x00000000, 230 regk_ddr2_dll_dis = 0x00000001, 231 regk_ddr2_dll_en = 0x00000000, 232 regk_ddr2_dll_rst = 0x00000100, 233 regk_ddr2_emrs = 0x00000081, 234 regk_ddr2_emrs2 = 0x00000082, 235 regk_ddr2_emrs3 = 0x00000083, 236 regk_ddr2_full = 0x00000001, 237 regk_ddr2_hi_ref_rate = 0x00000080, 238 regk_ddr2_mrs = 0x00000080, 239 regk_ddr2_no = 0x00000000, 240 regk_ddr2_nop = 0x000000b8, 241 regk_ddr2_ocd_adj = 0x00000200, 242 regk_ddr2_ocd_default = 0x00000380, 243 regk_ddr2_ocd_drive0 = 0x00000100, 244 regk_ddr2_ocd_drive1 = 0x00000080, 245 regk_ddr2_ocd_exit = 0x00000000, 246 regk_ddr2_odt_dis = 0x00000000, 247 regk_ddr2_offs = 0x00000000, 248 regk_ddr2_pre = 0x00000090, 249 regk_ddr2_pre_all = 0x00000400, 250 regk_ddr2_pwr_down_fast = 0x00000000, 251 regk_ddr2_pwr_down_slow = 0x00001000, 252 regk_ddr2_ref = 0x00000088, 253 regk_ddr2_rtt150 = 0x00000040, 254 regk_ddr2_rtt50 = 0x00000044, 255 regk_ddr2_rtt75 = 0x00000004, 256 regk_ddr2_rw_cfg_default = 0x00186000, 257 regk_ddr2_rw_dll_ctrl_default = 0x00000000, 258 regk_ddr2_rw_dll_ctrl_size = 0x00000004, 259 regk_ddr2_rw_dqs_dll_ctrl_default = 0x00000000, 260 regk_ddr2_rw_dqs_dll_ctrl_size = 0x00000004, 261 regk_ddr2_rw_latency_default = 0x00000000, 262 regk_ddr2_rw_phy_cfg_default = 0x00000000, 263 regk_ddr2_rw_pwr_down_default = 0x00000000, 264 regk_ddr2_rw_timing_default = 0x00000000, 265 regk_ddr2_s1Gb = 0x0000001a, 266 regk_ddr2_s256Mb = 0x0000000f, 267 regk_ddr2_s2Gb = 0x00000027, 268 regk_ddr2_s4Gb = 0x00000042, 269 regk_ddr2_s512Mb = 0x00000015, 270 regk_ddr2_temp0_85 = 0x00000618, 271 regk_ddr2_temp85_95 = 0x0000030c, 272 regk_ddr2_term150 = 0x00000002, 273 regk_ddr2_term50 = 0x00000003, 274 regk_ddr2_term75 = 0x00000001, 275 regk_ddr2_test = 0x00000080, 276 regk_ddr2_weak = 0x00000000, 277 regk_ddr2_wr2 = 0x00000200, 278 regk_ddr2_wr3 = 0x00000400, 279 regk_ddr2_yes = 0x00000001 280 }; 281 #endif /* __ddr2_defs_h */ 282