| /arch/powerpc/xmon/ |
| D | ppc-opc.c | 422 #define RT RS macro
1982 { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1983 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1984 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1985 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1986 { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1987 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1988 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1989 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1990 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
[all …]
|
| /arch/mips/mm/ |
| D | uasm.c | 27 RT = 0x002, enumerator
86 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
87 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
88 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
89 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
90 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
91 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
96 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
97 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
98 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
[all …]
|
| /arch/parisc/lib/ |
| D | fixup.S | 30 LDREG RT%__per_cpu_offset(%r1),\t1
40 LDREG RT%per_cpu__exception_data(%r1),\t1
50 LDREG RT%per_cpu__exception_data(%r1),\t2
|
| /arch/mips/kernel/ |
| D | traps.c | 454 #define RT 0x001f0000 macro
507 regs->regs[(opcode & RT) >> 16] = value; in simulate_ll()
530 reg = (opcode & RT) >> 16; in simulate_sc()
580 int rt = (opcode & RT) >> 16; in simulate_rdhwr()
|
| /arch/powerpc/kernel/ |
| D | misc_64.S | 305 #define LBZCIX(RT,RA,RB) .long (0x7c0006aa|(RT<<21)|(RA<<16)|(RB << 11)) argument
|
| /arch/arm/mach-sa1100/ |
| D | sleep.S | 139 @ Step 1 clear RT field of all MSCx registers
|
| /arch/x86/ |
| D | Kconfig | 718 entry in the chipset's IO-APIC is masked (as, e.g. the RT
|