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Searched refs:R_IMR_MAILBOX_CPU (Results 1 – 2 of 2) sorted by relevance

/arch/mips/sibyte/sb1250/
Dsmp.c43 IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU),
44 IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU)
/arch/mips/include/asm/sibyte/
Dsb1250_regs.h727 #define R_IMR_MAILBOX_CPU 0x00c0 macro