Home
last modified time | relevance | path

Searched refs:R_IMR_MAILBOX_SET_CPU (Results 1 – 2 of 2) sorted by relevance

/arch/mips/sibyte/sb1250/
Dsmp.c33 IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU),
34 IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU)
/arch/mips/include/asm/sibyte/
Dsb1250_regs.h729 #define R_IMR_MAILBOX_SET_CPU 0x00C8 macro