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Searched refs:SC (Results 1 – 12 of 12) sorted by relevance

/arch/m68k/fpsp040/
Dsetox.S696 movew %d0,SC(%a6) | ...SC is 2^(M) in extended
697 clrw SC+2(%a6)
698 movel #0x80000000,SC+4(%a6)
699 clrl SC+8(%a6)
762 fmulx SC(%a6),%fp0
776 movel #0x80010000,SC(%a6) | ...SC is -2^(-16382)
777 movel #0x80000000,SC+4(%a6)
778 clrl SC+8(%a6)
781 faddx SC(%a6),%fp0
789 movel #0x80010000,SC(%a6)
[all …]
/arch/s390/math-emu/
Dmath.c1208 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SC); FP_DECL_S(SR); in emu_maebr()
1215 FP_UNPACK_SP(SC, &current->thread.fp_regs.fprs[rz].f); in emu_maebr()
1217 FP_ADD_S(SR, SR, SC); in emu_maebr()
1224 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SC); FP_DECL_S(SR); in emu_maeb()
1231 FP_UNPACK_SP(SC, &current->thread.fp_regs.fprs[rz].f); in emu_maeb()
1233 FP_ADD_S(SR, SR, SC); in emu_maeb()
1272 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SC); FP_DECL_S(SR); in emu_msebr()
1279 FP_UNPACK_SP(SC, &current->thread.fp_regs.fprs[rz].f); in emu_msebr()
1281 FP_SUB_S(SR, SR, SC); in emu_msebr()
1288 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SC); FP_DECL_S(SR); in emu_mseb()
[all …]
/arch/sparc/lib/
Dudiv.S74 ! The number of bits in the result here is N*ITER+SC, where SC <= N.
Durem.S72 ! The number of bits in the result here is N*ITER+SC, where SC <= N.
Dsdiv.S88 ! The number of bits in the result here is N*ITER+SC, where SC <= N.
Drem.S88 ! The number of bits in the result here is N*ITER+SC, where SC <= N.
/arch/mips/
DKconfig1339 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
1345 # CPU may reorder reads and writes beyond LL/SC
1346 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1717 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
/arch/mips/kernel/
Dtraps.c457 #define SC 0xe0000000 macro
564 if ((opcode & OPCODE) == SC) in simulate_llsc()
/arch/m68k/ifpsp060/src/
Dfplsp.S7330 mov.w %d1,SC(%a6) # SC is 2^(M) in extended
7331 mov.l &0x80000000,SC+4(%a6)
7332 clr.l SC+8(%a6)
7392 fmul.x SC(%a6),%fp0
7405 mov.l &0x80010000,SC(%a6) # SC is -2^(-16382)
7406 mov.l &0x80000000,SC+4(%a6)
7407 clr.l SC+8(%a6)
7411 fadd.x SC(%a6),%fp0
7418 mov.l &0x80010000,SC(%a6)
7419 mov.l &0x80000000,SC+4(%a6)
[all …]
Dfpsp.S7203 set SC,FP_SCR0
/arch/powerpc/xmon/
Dppc-opc.c1639 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) macro
2816 { "sc", SC(17,1,0), SC_MASK, PPC, { LEV } },
2817 { "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
2818 { "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
2819 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2820 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
/arch/x86/
DKconfig1921 NSC Geode SC-1100's buggy TSC, which loses time when the