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Searched refs:SDRAM_IGENERIC (Results 1 – 2 of 2) sorted by relevance

/arch/blackfin/include/asm/
Dcplb.h35 #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) macro
36 #define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
65 #define L2_IMEMORY (SDRAM_IGENERIC)
/arch/blackfin/kernel/cplb-nompu/
Dcplbinit.c71 i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB; in generate_cplb_tables_cpu()
147 icplb_bounds[i_i++].data = SDRAM_IGENERIC; in generate_cplb_tables_all()
157 SDRAM_IGENERIC : SDRAM_INON_CHBL); in generate_cplb_tables_all()
164 icplb_bounds[i_i++].data = SDRAM_IGENERIC; in generate_cplb_tables_all()