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Searched refs:SIC_ISR0 (Results 1 – 8 of 8) sorted by relevance

/arch/blackfin/mach-bf518/include/mach/
DcdefBF51x_base.h78 #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
79 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
80 #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
81 #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
DdefBF51x_base.h57 #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ macro
/arch/blackfin/mach-bf527/include/mach/
DcdefBF52x_base.h78 #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
79 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
80 #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
81 #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
DdefBF52x_base.h60 #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ macro
/arch/blackfin/mach-bf538/include/mach/
DcdefBF538.h66 #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
67 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
70 #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0))
71 #define bfin_write_SIC_ISR(x, val) bfin_write32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0), val)
DdefBF539.h78 #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ macro
/arch/blackfin/mach-bf548/include/mach/
DcdefBF54x_base.h76 #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
77 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
82 #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2))
83 #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val)
DdefBF54x_base.h65 #define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */ macro