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Searched refs:SPORT3_MRCS0 (Results 1 – 4 of 4) sorted by relevance

/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h1041 #define SPORT3_MRCS0 0xffc02650 /* SPORT3 Multi channel Receive Select Regis… macro
DcdefBF54x_base.h1776 #define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
1777 #define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
/arch/blackfin/mach-bf538/include/mach/
DdefBF539.h833 #define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi-Channel Receive Select Register 0 */ macro
DcdefBF538.h416 #define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
417 #define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)