1 /* 2 * Copyright (C) 2004-2006 Atmel Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 #ifndef __ASM_AVR32_PTRACE_H 9 #define __ASM_AVR32_PTRACE_H 10 11 #define PTRACE_GETREGS 12 12 #define PTRACE_SETREGS 13 13 14 /* 15 * Status Register bits 16 */ 17 #define SR_H 0x20000000 18 #define SR_J 0x10000000 19 #define SR_DM 0x08000000 20 #define SR_D 0x04000000 21 #define MODE_NMI 0x01c00000 22 #define MODE_EXCEPTION 0x01800000 23 #define MODE_INT3 0x01400000 24 #define MODE_INT2 0x01000000 25 #define MODE_INT1 0x00c00000 26 #define MODE_INT0 0x00800000 27 #define MODE_SUPERVISOR 0x00400000 28 #define MODE_USER 0x00000000 29 #define MODE_MASK 0x01c00000 30 #define SR_EM 0x00200000 31 #define SR_I3M 0x00100000 32 #define SR_I2M 0x00080000 33 #define SR_I1M 0x00040000 34 #define SR_I0M 0x00020000 35 #define SR_GM 0x00010000 36 37 #define SR_H_BIT 29 38 #define SR_J_BIT 28 39 #define SR_DM_BIT 27 40 #define SR_D_BIT 26 41 #define MODE_SHIFT 22 42 #define SR_EM_BIT 21 43 #define SR_I3M_BIT 20 44 #define SR_I2M_BIT 19 45 #define SR_I1M_BIT 18 46 #define SR_I0M_BIT 17 47 #define SR_GM_BIT 16 48 49 /* The user-visible part */ 50 #define SR_L 0x00000020 51 #define SR_Q 0x00000010 52 #define SR_V 0x00000008 53 #define SR_N 0x00000004 54 #define SR_Z 0x00000002 55 #define SR_C 0x00000001 56 57 #define SR_L_BIT 5 58 #define SR_Q_BIT 4 59 #define SR_V_BIT 3 60 #define SR_N_BIT 2 61 #define SR_Z_BIT 1 62 #define SR_C_BIT 0 63 64 /* 65 * The order is defined by the stmts instruction. r0 is stored first, 66 * so it gets the highest address. 67 * 68 * Registers 0-12 are general-purpose registers (r12 is normally used for 69 * the function return value). 70 * Register 13 is the stack pointer 71 * Register 14 is the link register 72 * Register 15 is the program counter (retrieved from the RAR sysreg) 73 */ 74 #define FRAME_SIZE_FULL 72 75 #define REG_R12_ORIG 68 76 #define REG_R0 64 77 #define REG_R1 60 78 #define REG_R2 56 79 #define REG_R3 52 80 #define REG_R4 48 81 #define REG_R5 44 82 #define REG_R6 40 83 #define REG_R7 36 84 #define REG_R8 32 85 #define REG_R9 28 86 #define REG_R10 24 87 #define REG_R11 20 88 #define REG_R12 16 89 #define REG_SP 12 90 #define REG_LR 8 91 92 #define FRAME_SIZE_MIN 8 93 #define REG_PC 4 94 #define REG_SR 0 95 96 #ifndef __ASSEMBLY__ 97 struct pt_regs { 98 /* These are always saved */ 99 unsigned long sr; 100 unsigned long pc; 101 102 /* These are sometimes saved */ 103 unsigned long lr; 104 unsigned long sp; 105 unsigned long r12; 106 unsigned long r11; 107 unsigned long r10; 108 unsigned long r9; 109 unsigned long r8; 110 unsigned long r7; 111 unsigned long r6; 112 unsigned long r5; 113 unsigned long r4; 114 unsigned long r3; 115 unsigned long r2; 116 unsigned long r1; 117 unsigned long r0; 118 119 /* Only saved on system call */ 120 unsigned long r12_orig; 121 }; 122 123 #ifdef __KERNEL__ 124 125 #include <asm/ocd.h> 126 127 #define arch_ptrace_attach(child) ocd_enable(child) 128 129 #define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER) 130 #define instruction_pointer(regs) ((regs)->pc) 131 #define profile_pc(regs) instruction_pointer(regs) 132 133 extern void show_regs (struct pt_regs *); 134 valid_user_regs(struct pt_regs * regs)135static __inline__ int valid_user_regs(struct pt_regs *regs) 136 { 137 /* 138 * Some of the Java bits might be acceptable if/when we 139 * implement some support for that stuff... 140 */ 141 if ((regs->sr & 0xffff0000) == 0) 142 return 1; 143 144 /* 145 * Force status register flags to be sane and report this 146 * illegal behaviour... 147 */ 148 regs->sr &= 0x0000ffff; 149 return 0; 150 } 151 152 153 #endif /* __KERNEL__ */ 154 155 #endif /* ! __ASSEMBLY__ */ 156 157 #endif /* __ASM_AVR32_PTRACE_H */ 158