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Searched refs:TWI0_INT_STAT (Results 1 – 3 of 3) sorted by relevance

/arch/blackfin/mach-bf538/include/mach/
DdefBF539.h433 #define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */ macro
446 #define TWI0_INT_SRC TWI0_INT_STAT
DcdefBF538.h1276 #define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
1277 #define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h138 #define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */ macro