Searched refs:UART_CLK (Results 1 – 4 of 4) sorted by relevance
95 #define UART_CLK 1843200 macro99 #define UART_CLK (8000000 / 16) /* ( 3072000 / 16) */ macro107 .uartclk = UART_CLK, \
160 #define UART_CLK (1843200) /* 1.8432 MHz */ macro161 #define UART_BAUD(x) (UART_CLK / (16 * (x)))
80 sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK); in save_core_regs()200 au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync(); in restore_core_regs()
1251 #define UART_CLK 0x28 /* Baud Rate Clock Divider */ macro