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Searched refs:UART_LCR (Results 1 – 11 of 11) sorted by relevance

/arch/powerpc/platforms/embedded6xx/
Dls_uart.c66 out_8(avr_addr + UART_LCR, cval); /* initialise UART */ in avr_uart_configure()
72 out_8(avr_addr + UART_LCR, cval); /* Set character format */ in avr_uart_configure()
74 out_8(avr_addr + UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */ in avr_uart_configure()
77 out_8(avr_addr + UART_LCR, cval); /* reset DLAB */ in avr_uart_configure()
/arch/powerpc/boot/
Dvirtex.c21 #define UART_LCR 3 /* Out: Line Control Register */ macro
58 out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_DLAB); in virtex_ns16550_console_init()
65 out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_WLEN8); in virtex_ns16550_console_init()
Dns16550.c21 #define UART_LCR 3 /* Out: Line Control Register */ macro
/arch/frv/kernel/
Dgdb-io.h24 #undef UART_LCR
37 #define UART_LCR 3*8 /* Out: Line Control Register */ macro
/arch/mips/alchemy/common/
Dpower.c79 sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR); in save_core_regs()
199 au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync(); in restore_core_regs()
/arch/sh/include/asm/
Dsmc37c93x.h61 #define UART_LCR 0x6 /* Line Control Register */ macro
/arch/mips/cavium-octeon/
Dserial.c44 if (offset == UART_LCR) in octeon_serial_out()
/arch/arm/mach-aaec2000/include/mach/
Daaec2000.h77 #define UART_LCR 0x04 macro
/arch/blackfin/mach-bf533/include/mach/
DcdefBF532.h493 #define bfin_read_UART_LCR() bfin_read16(UART_LCR)
494 #define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
/arch/mips/include/asm/mach-au1x00/
Dau1000.h1247 #define UART_LCR 0x14 /* Line Control Register */ macro
/arch/blackfin/mach-bf561/include/mach/
DcdefBF561.h165 #define bfin_read_UART_LCR() bfin_read16(UART_LCR)
166 #define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)