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Searched refs:__FPU_FPSCR (Results 1 – 12 of 12) sorted by relevance

/arch/powerpc/math-emu/
Dmtfsf.c39 __FPU_FPSCR &= ~(mask); in mtfsf()
40 __FPU_FPSCR |= (frB[1] & mask); in mtfsf()
42 __FPU_FPSCR &= ~(FPSCR_VX); in mtfsf()
43 if (__FPU_FPSCR & (FPSCR_VXSNAN | FPSCR_VXISI | FPSCR_VXIDI | in mtfsf()
46 __FPU_FPSCR |= FPSCR_VX; in mtfsf()
48 fpscr = __FPU_FPSCR; in mtfsf()
56 __FPU_FPSCR = fpscr; in mtfsf()
59 printk("%s: %02x %p: %08lx\n", __func__, FM, frB, __FPU_FPSCR); in mtfsf()
Dfctiwz.c17 fpscr = __FPU_FPSCR; in fctiwz()
18 __FPU_FPSCR &= ~(3); in fctiwz()
19 __FPU_FPSCR |= FP_RND_ZERO; in fctiwz()
25 __FPU_FPSCR = fpscr; in fctiwz()
Dmtfsfi.c16 __FPU_FPSCR &= ~(mask << ((7 - crfD) << 2)); in mtfsfi()
17 __FPU_FPSCR |= (IMM & 0xf) << ((7 - crfD) << 2); in mtfsfi()
20 printk("%s: %d %x: %08lx\n", __func__, crfD, IMM, __FPU_FPSCR); in mtfsfi()
Dmtfsb1.c12 __FPU_FPSCR |= (1 << (31 - crbD)); in mtfsb1()
15 printk("%s: %d %08lx\n", __func__, crbD, __FPU_FPSCR); in mtfsb1()
Dmtfsb0.c12 __FPU_FPSCR &= ~(1 << (31 - crbD)); in mtfsb0()
15 printk("%s: %d %08lx\n", __func__, crbD, __FPU_FPSCR); in mtfsb0()
Dmcrfs.c21 value = (__FPU_FPSCR >> ((7 - crfS) << 2)) & 15; in mcrfs()
22 __FPU_FPSCR &= ~(clear); in mcrfs()
Dfcmpu.c33 __FPU_FPSCR &= ~(0x1f000); in fcmpu()
34 __FPU_FPSCR |= (cmp << 12); in fcmpu()
Dfcmpo.c36 __FPU_FPSCR &= ~(0x1f000); in fcmpo()
37 __FPU_FPSCR |= (cmp << 12); in fcmpo()
Dmffs.c11 frD[1] = __FPU_FPSCR; in mffs()
Dmath_efp.c211 __FPU_FPSCR = mfspr(SPRN_SPEFSCR); in do_spe_mathemu()
214 printk("speinsn:%08lx spefscr:%08lx\n", speinsn, __FPU_FPSCR); in do_spe_mathemu()
636 __FPU_FPSCR &= ~FP_EX_MASK; in do_spe_mathemu()
637 __FPU_FPSCR |= (FP_CUR_EXCEPTIONS & FP_EX_MASK); in do_spe_mathemu()
638 mtspr(SPRN_SPEFSCR, __FPU_FPSCR); in do_spe_mathemu()
646 FP_CUR_EXCEPTIONS, __FPU_FPSCR); in do_spe_mathemu()
679 __FPU_FPSCR = mfspr(SPRN_SPEFSCR); in speround_handler()
Dmath.c159 fpscr = __FPU_FPSCR; in record_exception()
207 __FPU_FPSCR = fpscr; in record_exception()
466 regs->ccr |= (__FPU_FPSCR >> 4) & 0x0f000000; in do_mathemu()
/arch/powerpc/include/asm/
Dsfp-machine.h108 #define __FPU_FPSCR (current->thread.spefscr) macro
111 (__FPU_FPSCR >> 2) & 0x1f; \
128 #define __FPU_FPSCR (current->thread.fpscr.val) macro
135 (__FPU_FPSCR >> 3) & 0x1f; \
198 __FPU_FPSCR & 0x3; \