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Searched refs:__REG2 (Results 1 – 14 of 14) sorted by relevance

/arch/arm/mach-ns9xxx/include/mach/
Dregs-mem.h73 #define MEM_DMCONF(x) __REG2(0xa0700100, (x) << 3)
76 #define MEM_DMRCD(x) __REG2(0xa0700104, (x) << 3)
79 #define MEM_SMC(x) __REG2(0xa0700200, (x) << 3)
118 #define MEM_SMWED(x) __REG2(0xa0700204, (x) << 3)
121 #define MEM_SMOED(x) __REG2(0xa0700208, (x) << 3)
124 #define MEM_SMRD(x) __REG2(0xa070020c, (x) << 3)
127 #define MEM_SMPMRD(x) __REG2(0xa0700210, (x) << 3)
130 #define MEM_SMWD(x) __REG2(0xa0700214, (x) << 3)
133 #define MEM_SWT(x) __REG2(0xa0700218, (x) << 3)
Dregs-sys-ns9360.h22 #define SYS_BRC(x) __REG2(0xa0900004, (x))
25 #define SYS_TRC(x) __REG2(0xa0900044, (x))
28 #define SYS_TR(x) __REG2(0xa0900084, (x))
48 #define SYS_TC(x) __REG2(0xa0900190, (x))
104 #define SYS_SMCSDMB(x) __REG2(0xa09001d0, (x) << 1)
107 #define SYS_SMCSDMM(x) __REG2(0xa09001d4, (x) << 1)
110 #define SYS_SMCSSMB(x) __REG2(0xa09001f0, (x) << 1)
116 #define SYS_SMCSSMM(x) __REG2(0xa09001f4, (x) << 1)
130 #define SYS_EIC(x) __REG2(0xa0900214, (x))
Dregs-sys-common.h17 #define SYS_IVA(x) __REG2(0xa09000c4, (x))
20 #define SYS_IC(x) __REG2(0xa0900144, (x))
Dregs-bbu.h22 #define BBU_GCONFb1(x) __REG2(0x90600010, (x))
23 #define BBU_GCONFb2(x) __REG2(0x90600100, (x))
Dhardware.h37 # define __REG2(x, y) ((void __iomem __force *)(io_p2v((x)) + 4 * (y))) macro
73 # define __REG2(x, y) io_p2v((x) + 4 * (y)) macro
/arch/arm/mach-pxa/include/mach/
Dpxa-regs.h73 #define DCSR(x) __REG2(0x40000000, (x) << 2)
98 &__REG2(0x40000100, ((n) & 0x3f) << 2) : \
99 &__REG2(0x40001100, ((n) & 0x3f) << 2)))
104 #define DDADR(x) __REG2(0x40000200, (x) << 4)
105 #define DSADR(x) __REG2(0x40000204, (x) << 4)
106 #define DTADR(x) __REG2(0x40000208, (x) << 4)
107 #define DCMD(x) __REG2(0x4000020c, (x) << 4)
244 #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
245 #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
246 #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
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Dpxa2xx-regs.h44 #define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing…
45 #define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Con…
46 #define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configura…
114 #define PCMD(x) __REG2(0x40F00080, (x)<<2)
Dpxa27x-udc.h102 #define UDCCSN(x) __REG2(0x40600100, (x) << 2)
149 #define UDCBCN(x) __REG2(0x40600200, (x)<<2)
175 #define UDCDN(x) __REG2(0x40600300, (x)<<2)
203 #define UDCCN(x) __REG2(0x40600400, (x)<<2)
Dhardware.h51 # define __REG2(x,y) \ macro
/arch/arm/mach-imx/include/mach/
Dimx-regs.h62 #define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)
63 #define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)
64 #define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)
65 #define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)
66 #define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)
67 #define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)
68 #define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)
69 #define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)
70 #define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8)
71 #define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8)
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Dhardware.h29 # define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) macro
/arch/arm/mach-lh7a40x/include/mach/
Dhardware.h50 # define __REG2(x,y) \ macro
/arch/arm/mach-pxa/
Dmfp-pxa2xx.c30 #define PGSR(x) __REG2(0x40F00020, (x) << 2)
31 #define __GAFR(u, x) __REG2((u) ? 0x40E00058 : 0x40E00054, (x) << 3)
/arch/xtensa/include/asm/
Dcoprocessor.h120 #define __REG2(cc,abi,type,...) __REG2_ ## type (__VA_ARGS__) macro