Home
last modified time | relevance | path

Searched refs:____cacheline_aligned_in_smp (Results 1 – 6 of 6) sorted by relevance

/arch/ia64/include/asm/sn/
Dnodepda.h56 spinlock_t ptc_lock ____cacheline_aligned_in_smp; member
/arch/powerpc/include/asm/
Dthread_info.h42 unsigned long flags ____cacheline_aligned_in_smp; member
/arch/x86/include/asm/
Dpda.h40 } ____cacheline_aligned_in_smp; variable
Duaccess.h443 } ____cacheline_aligned_in_smp movsl_mask;
/arch/blackfin/mm/
Dsram-alloc.c45 static DEFINE_PER_CPU(spinlock_t, l1sram_lock) ____cacheline_aligned_in_smp;
46 static DEFINE_PER_CPU(spinlock_t, l1_data_sram_lock) ____cacheline_aligned_in_smp;
47 static DEFINE_PER_CPU(spinlock_t, l1_inst_sram_lock) ____cacheline_aligned_in_smp;
48 static spinlock_t l2_sram_lock ____cacheline_aligned_in_smp; variable
/arch/mips/mm/
Dpage.c623 } ____cacheline_aligned_in_smp page_descr[DM_NUM_CHANNELS];